[Commit-gnuradio] r7226 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2007-12-18 11:01:57 -0700 (Tue, 18 Dec 2007)
New Revision: 7226

Added:
   usrp2/trunk/fpga/sdr_lib/hb_tb.v
Modified:
   usrp2/trunk/fpga/sdr_lib/
   usrp2/trunk/fpga/sdr_lib/hb_decim.v
Log:
progress



Property changes on: usrp2/trunk/fpga/sdr_lib
___________________________________________________________________
Name: svn:ignore
   - db
*.vcd
   + a.out
db
*.vcd


Modified: usrp2/trunk/fpga/sdr_lib/hb_decim.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_decim.v 2007-12-18 00:57:11 UTC (rev 7225)
+++ usrp2/trunk/fpga/sdr_lib/hb_decim.v 2007-12-18 18:01:57 UTC (rev 7226)
@@ -1,23 +1,24 @@
 
 `define SET_COEFF  124
+`define SET_TABLE  125
 
 module hb_decim
-  #(parameter SWIDTH = 16,
-    parameter CWIDTH = 16,
+  #(parameter SWIDTH = 17,
+    parameter CWIDTH = 18,
     parameter TWIDTH = 16,
     parameter ACC_WIDTH = 40)
     (input clk, input rst,
      input set_stb, input [7:0] set_addr, input [31:0] set_data,
      input [SWIDTH-1:0] sample_in,
      input strobe_in,
-     output [SWIDTH-1:0] sample_out.
+     output [SWIDTH-1:0] sample_out,
      output strobe_out 
      );
 
-   reg [3:0] even_addr, odd_addr_a, odd_addr_b;
+   reg [3:0] even_addr, odd_addr_a, odd_addr_b, coeff_addr;
    genvar    i;
    
-   wire [SWIDTH-1:0] cascade, even_sample, odd_sample_a, odd_sample_b, odd_sum;
+   wire [SWIDTH-1:0] cascade, even_sample, odd_sample_a, odd_sample_b;
    wire [SWIDTH:0]   odd_sum = {odd_sample_a[SWIDTH-1],odd_sample_a} 
                     + {odd_sample_b[SWIDTH-1],odd_sample_b};
 
@@ -26,19 +27,24 @@
    wire             write_table = (set_addr == `SET_TABLE) & set_stb;
 
    wire [TWIDTH-1:0] control_word;
+   reg [3:0]        phase;
+   wire             write_even, write_odd;
+   wire             signed [35:0]           product;
+   reg                      signed [ACC_WIDTH-1:0] accum;
+   wire             clear_accum = 0;
    
    generate
       for (i=0;i<TWIDTH;i=i+1)
        begin : gen_table_srl
           SRLC16E
-            srlc_table(.Q(control_word),.Q15(),
+            srlc_table(.Q(control_word[i]),.Q15(),
                        .A0(phase[0]),.A1(phase[1]),.A2(phase[2]),.A3(phase[3]),
                        .CE(write_table),.CLK(clk),.D(set_data[i]));
        end
    endgenerate
               
    generate
-      for (i=0;i<CWDITH;i=i+1)
+      for (i=0;i<CWIDTH;i=i+1)
        begin : gen_coeff_srl
           SRLC16E
             srlc_coeff(.Q(odd_coeff[i]),.Q15(even_coeff[i]),
@@ -55,7 +61,7 @@
                      
.A0(even_addr[0]),.A1(even_addr[1]),.A2(even_addr[2]),.A3(even_addr[3]),
                      .CE(write_even),.CLK(clk),.D(sample_in[i]));
           SRLC16E
-            srlc_odd_a(.Q(odd_sample_a[i]),.Q15(cascade[i])
+            srlc_odd_a(.Q(odd_sample_a[i]),.Q15(cascade[i]),
                        
.A0(odd_addr_a[0]),.A1(odd_addr_a[1]),.A2(odd_addr_a[2]),.A3(odd_addr_a[3]),
                        .CE(write_odd),.CLK(clk),.D(sample_in[i]));
           SRL16E
@@ -65,10 +71,20 @@
        end
    endgenerate
 
-   reg [
-   reg [3:0] phase;
+   
    always @(posedge clk)
      if(rst)
        phase <= 0;
-       phase < = 0
+
+   MULT18X18S mult(.P(product),.A(odd_coeff),.B(odd_sum),.C(clk),.CE(1),.R(0));
+
+   always @(posedge clk)
+     if(rst)
+       accum <= 0;
+     else if(clear_accum)
+       accum <= 0;
+     else
+       accum <= accum + product;
+
 endmodule // hb_decim
+

Added: usrp2/trunk/fpga/sdr_lib/hb_tb.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_tb.v                            (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/hb_tb.v    2007-12-18 18:01:57 UTC (rev 7226)
@@ -0,0 +1,53 @@
+
+module hb_tb();
+
+   localparam SWIDTH = 17;
+   localparam CWIDTH = 18;
+   localparam TWIDTH = 16;
+   localparam ACC_WIDTH = 40;
+   
+   reg clk = 0, rst = 1;
+   wire strobe_in, strobe_out;
+   reg [SWIDTH-1:0] sample_in;
+   wire [SWIDTH-1:0] sample_out;
+
+   reg                set_stb;
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+
+   localparam  DECIM = 15;
+   
+   initial $dumpfile("hb_tb.vcd");
+   initial $dumpvars(0,hb_tb);
+
+   always #5 clk <= ~clk;
+   initial 
+     begin
+       @(posedge clk);
+       @(negedge clk);
+       rst <= 0;
+     end
+
+   reg [7:0] stb_counter;
+   always @(posedge clk)
+     if(rst)
+       stb_counter <= 0;
+     else
+       if(stb_counter == 0)
+        stb_counter <= DECIM;
+       else
+        stb_counter <= stb_counter - 1;
+   assign    strobe_in = (stb_counter == 0);
+   
+   hb_decim #(.SWIDTH(SWIDTH),.CWIDTH(CWIDTH),
+             .TWIDTH(TWIDTH),.ACC_WIDTH(ACC_WIDTH)) hb_decim
+     (.clk(clk), .rst(rst),
+      .set_stb(set_stb), .set_addr(), .set_data(),
+      .sample_in(sample_in),
+      .strobe_in(strobe_in),
+      .sample_out(sample_out),
+      .strobe_out(strobe_out)
+      );
+
+   
+endmodule // hb_tb