[Commit-gnuradio] r7187 - usrp2/trunk/firmware/apps

[eb]

Author: eb
Date: 2007-12-14 19:41:34 -0700 (Fri, 14 Dec 2007)
New Revision: 7187

Added:
   usrp2/trunk/firmware/apps/tx_only.c
Modified:
   usrp2/trunk/firmware/apps/Makefile.am
Log:
work-in-progress on tx

Modified: usrp2/trunk/firmware/apps/Makefile.am
===================================================================
--- usrp2/trunk/firmware/apps/Makefile.am       2007-12-15 00:33:46 UTC (rev 
7186)
+++ usrp2/trunk/firmware/apps/Makefile.am       2007-12-15 02:41:34 UTC (rev 
7187)
@@ -36,4 +36,6 @@
        test_phy_comm \
        test_printf \
        timer_test \
-       test_serdes
+       test_serdes \
+       tx_only
+

Copied: usrp2/trunk/firmware/apps/tx_only.c (from rev 7186, 
usrp2/trunk/firmware/apps/rx_only.c)
===================================================================
--- usrp2/trunk/firmware/apps/tx_only.c                         (rev 0)
+++ usrp2/trunk/firmware/apps/tx_only.c 2007-12-15 02:41:34 UTC (rev 7187)
@@ -0,0 +1,505 @@
+/*
+ * Copyright 2007 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "u2_init.h"
+#include "memory_map.h"
+#include "spi.h"
+#include "hal_io.h"
+#include "buffer_pool.h"
+#include "pic.h"
+#include "bool.h"
+#include "eth_driver.h"
+#include "eth_mac.h"
+#include "nonstdio.h"
+#include "usrp2_eth_packet.h"
+#include "memcpy_wa.h"
+#include "dbsm.h"
+#include <stddef.h>
+#include <stdlib.h>
+#include <string.h>
+
+#define        _AL4 __attribute__((aligned (4)))
+
+#define USE_BUFFER_INTERRUPT   0       // 0 or 1
+
+
+static int timer_delta = MASTER_CLK_RATE/1000; // tick at 1kHz
+
+/*
+ * This program can respond to queries from the host
+ * and stream rx samples.
+ *
+ * Buffer 1 is used by the cpu to send frames to the host.
+ * Buffers 2 and 3 are used to double-buffer the DSP Rx to eth flow
+ * Buffers 4 and 5 are used to double-buffer the eth to DSP Tx  eth flow
+ */
+//#define CPU_RX_BUF   0       // eth -> cpu
+#define CPU_TX_BUF     1       // cpu -> eth
+
+#define        DSP_RX_BUF_0    2       // dsp rx -> eth (double buffer)
+#define        DSP_RX_BUF_1    3       // dsp rx -> eth
+#define        DSP_TX_BUF_0    4       // eth -> dsp tx (double buffer)
+#define        DSP_TX_BUF_1    5       // eth -> dsp tx
+
+
+/*
+ * ================================================================
+ *      configure DSP RX double buffering state machine
+ * ================================================================
+ */
+
+#define LAST_LINE      255     // last line in buffer
+
+
+// 4 lines of ethernet hdr + 1 line (word0)
+// DSP Rx writes timestamp followed by nlines_per_frame of samples
+#define DSP_RX_FIRST_LINE                5
+#define DSP_RX_SAMPLES_PER_FRAME       128
+#define        DSP_RX_EXTRA_LINES                1     // writes timestamp
+
+// Receive from DSP Rx
+buf_cmd_args_t dsp_rx_recv_args = {
+  PORT_DSP,
+  DSP_RX_FIRST_LINE,
+  LAST_LINE
+};
+
+// send to ethernet
+buf_cmd_args_t dsp_rx_send_args = {
+  PORT_ETH,
+  0,           // starts with ethernet header in line 0
+  0,           // filled in from last_line register
+};
+
+dbsm_t dsp_rx_sm;      // the state machine
+
+/*
+ * ================================================================
+ *      configure DSP TX double buffering state machine
+ * ================================================================
+ */
+
+// 4 lines of ethernet hdr + 2 lines (word0 + timestamp)
+// DSP Tx reads word0 (flags) + timestamp followed by samples
+
+#define DSP_TX_FIRST_LINE                4
+#define DSP_TX_SAMPLES_PER_FRAME       250     // not used except w/ debugging
+#define        DSP_TX_EXTRA_LINES                2     // reads word0 + 
timestamp
+
+// Receive from ethernet
+buf_cmd_args_t dsp_tx_recv_args = {
+  PORT_ETH,
+  0,
+  LAST_LINE
+};
+
+// send to DSP Tx
+buf_cmd_args_t dsp_tx_send_args = {
+  PORT_DSP,
+  DSP_TX_FIRST_LINE,   // starts just past ethernet header
+  0                    // filled in from last_line register
+};
+
+dbsm_t dsp_tx_sm;      // the state machine
+
+/*
+ * send constant buffer to DSP TX
+ */
+static inline void 
+SEND_CONST_TO_DSP_TX(void)
+{
+  bp_send_from_buf(DSP_TX_BUF_0, PORT_DSP, 1,
+                  DSP_TX_FIRST_LINE,
+                  DSP_TX_FIRST_LINE + DSP_TX_EXTRA_LINES + 
DSP_TX_SAMPLES_PER_FRAME - 1);
+}
+
+// ----------------------------------------------------------------
+
+
+
+// The mac address of the host we're sending to.
+u2_mac_addr_t host_mac_addr;
+
+
+void link_changed_callback(int speed);
+static volatile bool link_is_up = false;       // eth handler sets this
+
+
+void
+timer_irq_handler(unsigned irq)
+{
+  hal_set_timeout(timer_delta);        // schedule next timeout
+}
+
+// Tx DSP underrun
+void
+underrun_irq_handler(unsigned irq)
+{
+  dsp_tx_regs->clear_state = 1;
+  bp_clear_buf(DSP_TX_BUF_0);
+  bp_clear_buf(DSP_TX_BUF_1);
+  dbsm_stop(&dsp_tx_sm);
+
+  // FIXME anything else?
+
+  putstr("\nirq: underrun\n");
+}
+
+// Rx DSP overrun
+void
+overrun_irq_handler(unsigned irq)
+{
+  dsp_rx_regs->clear_state = 1;
+  bp_clear_buf(DSP_RX_BUF_0);
+  bp_clear_buf(DSP_RX_BUF_1);
+  dbsm_stop(&dsp_rx_sm);
+
+  // FIXME anything else?
+
+  putstr("\nirq: overrun\n");
+}
+
+
+static void
+start_rx_cmd(const u2_mac_addr_t *host)
+{
+  // printf("start_rx_cmd\n");
+  // hal_toggle_leds(0x2);
+
+  host_mac_addr = *host;       // remember who we're sending to
+
+  /*
+   * Construct  ethernet header and word0 and preload into two buffers
+   */
+  u2_eth_packet_t      pkt;
+  memset(&pkt, 0, sizeof(pkt));
+  pkt.ehdr.dst = *host;
+  pkt.ehdr.ethertype = U2_ETHERTYPE;
+  u2p_set_word0(&pkt.fixed, 0, 0);
+  // DSP RX will fill in timestamp
+
+  memcpy_wordaligned(buffer_ram(DSP_RX_BUF_0), &pkt, sizeof(pkt));
+  memcpy_wordaligned(buffer_ram(DSP_RX_BUF_1), &pkt, sizeof(pkt));
+
+
+  // setup RX DSP regs
+  dsp_rx_regs->clear_state = 1;                // reset
+  dsp_rx_regs->freq = 0;
+  dsp_rx_regs->scale_iq = (1 << 16) | 1;
+  dsp_rx_regs->decim_rate = 63;        // register gets N - 1
+
+  uint32_t cmd = MK_RX_CMD(10000 * DSP_RX_SAMPLES_PER_FRAME, 
DSP_RX_SAMPLES_PER_FRAME);
+  // printf("rx_command = "); puthex32_nl(cmd);
+  dsp_rx_regs->rx_command = cmd;
+
+  // kick off the state machine
+  dbsm_start(&dsp_rx_sm);
+
+  // dsp_rx_regs->rx_time = 1; // timer_regs->time + 10000;
+  dsp_rx_regs->rx_time = T_NOW;                // start NOW!
+
+  // FIXME need to arrange to add additional stuff to cmd queue
+}
+
+
+static void
+stop_rx_cmd(void)
+{
+  dsp_rx_regs->clear_state = 1;        // FIXME need to flush cmd queue
+  bp_clear_buf(DSP_RX_BUF_0);
+  bp_clear_buf(DSP_RX_BUF_1);
+}
+
+static void
+start_tx_transfers(void)
+{
+  bp_clear_buf(DSP_TX_BUF_0);  // FIXME, really goes in state machine
+  bp_clear_buf(DSP_TX_BUF_1);
+
+  // fill everything with a constant 10k + 10kj
+
+  uint32_t const_sample = (10000 << 16) | 10000;
+  int i;
+  for (i = 0; i < BUFFER_POOL_BUFFER_SIZE; i++){
+    buffer_ram(DSP_TX_BUF_0)[i] = const_sample;
+    buffer_ram(DSP_TX_BUF_1)[i] = const_sample;
+  }
+
+  /*
+   * Construct  ethernet header and word0 and preload into two buffers
+   */
+  u2_eth_packet_t      pkt;
+  memset(&pkt, 0, sizeof(pkt));
+  //pkt.ehdr.dst = *host;
+  pkt.ehdr.ethertype = U2_ETHERTYPE;
+  u2p_set_word0(&pkt.fixed,
+               U2P_TX_IMMEDIATE | U2P_TX_START_OF_BURST | U2P_TX_END_OF_BURST,
+               0);
+  u2p_set_timestamp(&pkt.fixed, T_NOW);
+
+  memcpy_wordaligned(buffer_ram(DSP_TX_BUF_0), &pkt, sizeof(pkt));
+  memcpy_wordaligned(buffer_ram(DSP_TX_BUF_1), &pkt, sizeof(pkt));
+
+
+  int tx_scale = 256;
+
+  // setup Tx DSP regs
+  dsp_tx_regs->clear_state = 1;                // reset
+  dsp_tx_regs->freq = MASTER_CLK_RATE / 10000000;      // 10 MHz
+  dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
+  dsp_tx_regs->interp_rate = 19;       // register gets N - 1
+
+  // kick off the state machine
+  // dbsm_start(&dsp_rx_sm);
+
+  SEND_CONST_TO_DSP_TX();      // send constant buffer to DSP TX
+}
+
+static void
+set_reply_hdr(u2_eth_packet_t *reply_pkt, u2_eth_packet_t const *cmd_pkt)
+{
+  reply_pkt->ehdr.dst = cmd_pkt->ehdr.src;
+  reply_pkt->ehdr.ethertype = U2_ETHERTYPE;
+  reply_pkt->ehdr._pad = 0;
+  u2p_set_word0(&reply_pkt->fixed, 0, CONTROL_CHAN);
+  reply_pkt->fixed.timestamp = timer_regs->time;
+}
+
+static void
+handle_control_chan_frame(int bufno, u2_eth_packet_t *pkt, size_t len)
+{
+  static unsigned char payload[64] _AL4;
+  static unsigned char reply[sizeof(u2_eth_packet_t) + sizeof(u2_subpkt_t)] 
_AL4;
+  unsigned char *s = &reply[sizeof(u2_eth_packet_t)];
+  size_t reply_len = 0;
+  int   i;
+
+  // FIXME copy as needed...
+  // copy 64 bytes of payload into stack buffer
+  memcpy_wordaligned(payload,
+                    (unsigned char *) buffer_ram(bufno) + 
sizeof(u2_eth_packet_t),
+                    sizeof(payload));
+
+  unsigned char *p = payload;
+  int opcode = p[0];
+
+  switch(opcode){
+  case OP_ID:
+    memset(reply, 0, sizeof(reply));
+    set_reply_hdr((u2_eth_packet_t *) reply, pkt);
+    {
+      op_id_reply_t *r = (op_id_reply_t *) s;
+      reply_len = sizeof(u2_eth_packet_t) + sizeof(op_id_reply_t);
+      if (reply_len < 64)
+       reply_len = 64;
+      r->opcode = OP_ID_REPLY;
+      r->len = sizeof(op_id_reply_t);
+      r->rid_mbz = 0;          // FIXME
+      memcpy(&r->addr, eth_mac_addr(), 6);
+      r->hw_rev = 0x0000;      // FIXME
+      for (i = 0; i < sizeof(r->serial_no); i++)
+       r->serial_no[i] = '0';  // FIXME
+
+      // r->fpga_md5sum = ;    // FIXME
+      // r->sw_md5sum = ;      // FIXME
+    }
+
+    // FIXME need to see if ethernet tx is busy
+
+    // copy reply into CPU_TX_BUF
+    memcpy_wordaligned(buffer_ram(CPU_TX_BUF), reply, reply_len);
+
+    bp_send_from_buf(CPU_TX_BUF, PORT_ETH, 1, 0, reply_len / 4);
+    break;
+    
+  case OP_START_RX:
+    start_rx_cmd(&pkt->ehdr.src);
+    break;
+    
+  case OP_STOP_RX:
+    stop_rx_cmd();
+    break;
+    
+  default:
+    break;
+  }
+}
+
+static void
+handle_rcvd_eth_frame(int bufno)
+{
+  u2_eth_packet_t pkt;
+  size_t byte_len = (buffer_pool_status->last_line[bufno] - 1) * 4;
+
+  hal_toggle_leds(0x1);
+
+  // inspect rcvd frame and figure out what do do.
+
+  // copy first part of frame to stack buffer so we can byte address it
+  memcpy_wordaligned(&pkt, buffer_ram(bufno), sizeof(pkt));
+
+  if (pkt.ehdr.ethertype != U2_ETHERTYPE)
+    return;            // ignore, probably bogus PAUSE frame from MAC
+
+  int chan = u2p_chan(&pkt.fixed);
+  switch (chan){
+  case CONTROL_CHAN:
+    handle_control_chan_frame(bufno, &pkt, byte_len);
+    break;
+
+  case 0:      // to Tx DSP
+  default:
+    break;
+  }
+}
+
+void
+buffer_irq_handler(unsigned irq)
+{
+  uint32_t  status = buffer_pool_status->status;
+
+  if (0){
+    putstr("irq: ");
+    puthex32(status);
+    putchar('\n');
+  }
+
+  if (status & BPS_ERROR_ALL){
+    // FIXME rare path, handle error conditions
+  }
+
+  if (status & BPS_DONE(DSP_TX_BUF_0)){
+    bp_clear_buf(DSP_TX_BUF_0);
+    SEND_CONST_TO_DSP_TX();
+    hal_toggle_leds(0x1);
+  }
+
+#if 0
+  // FIXME probably ought to round-robin the check for done
+
+  if (status & BPS_DONE(CPU_RX_BUF)){  // we've rcvd a frame from ethernet
+    bp_clear_buf(CPU_RX_BUF);
+    handle_rcvd_eth_frame(CPU_RX_BUF);
+    bp_receive_to_buf(CPU_RX_BUF, PORT_ETH, 1, 0, 255);
+  }
+
+  if (status & BPS_DONE(CPU_TX_BUF)){
+    bp_clear_buf(CPU_TX_BUF);
+  }
+
+  dbsm_process_status(&dsp_rx_sm, status);
+#endif
+}
+
+int
+main(void)
+{
+  u2_init();
+
+  // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
+  hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
+  hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1);   // no printing...
+
+  putstr("\ntx_only\n");
+  
+  // Control LEDs
+  hal_set_leds(0x0, 0x3);
+
+  if (USE_BUFFER_INTERRUPT)
+    pic_register_handler(IRQ_BUFFER,   buffer_irq_handler);
+
+  pic_register_handler(IRQ_OVERRUN,  overrun_irq_handler);
+  pic_register_handler(IRQ_UNDERRUN, underrun_irq_handler);
+
+  //pic_register_handler(IRQ_TIMER, timer_irq_handler);
+  //hal_set_timeout(timer_delta);
+
+  eth_driver_register_link_changed_callback(link_changed_callback);
+
+  eth_mac_init();
+  eth_driver_init();
+
+  // initialize double buffering state machine for DSP RX -> Ethernet
+  dbsm_init(&dsp_rx_sm, DSP_RX_BUF_0, &dsp_rx_recv_args, &dsp_rx_send_args);
+
+
+  // setup receive from ETH
+  // bp_receive_to_buf(CPU_RX_BUF, PORT_ETH, 1, 0, 255);
+
+#if 0
+  if (hwconfig_simulation_p()){
+    // If we're simulating, pretend that we got a start command from the host
+    u2_mac_addr_t host = {{ 0x00, 0x0A, 0xE4, 0x3E, 0xD2, 0xD5 }};
+    start_rx_cmd(&host);
+  }
+#endif
+
+  start_tx_transfers();                // send constant buffers to DSP TX
+
+  while(1){
+    if (!USE_BUFFER_INTERRUPT)
+      buffer_irq_handler(0);
+  }
+}
+
+// ----------------------------------------------------------------
+
+// debugging output on tx pins
+#define LS_MASK  0xE0000
+#define LS_1000  0x80000
+#define LS_100   0x40000
+#define LS_10    0x20000
+
+/*
+ * Called when eth phy state changes (w/ interrupts disabled)
+ */
+void
+link_changed_callback(int speed)
+{
+  int v = 0;
+  switch(speed){
+  case 10:
+    v = LS_10;
+    link_is_up = true;
+    break;
+    
+  case 100:
+    v = LS_100;
+    link_is_up = true;
+    break;
+    
+  case 1000:
+    v = LS_100;
+    link_is_up = true;
+    break;
+
+  default:
+    v = 0;
+    link_is_up = false;
+    break;
+  }
+
+  hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */
+
+  // hal_set_leds(link_is_up ? 0x2 : 0x0, 0x2);
+
+  printf("\neth link changed: speed = %d\n", speed);
+}