[Commit-gnuradio] r7183 - gnuradio/branches/developers/gnychis/inband/usrp/fpga/inband_lib

[gnychis]

Author: gnychis
Date: 2007-12-14 15:04:34 -0700 (Fri, 14 Dec 2007)
New Revision: 7183

Modified:
   
gnuradio/branches/developers/gnychis/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
Log:
Work in progress on interleaving I&Q


Modified: 
gnuradio/branches/developers/gnychis/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
--- 
gnuradio/branches/developers/gnychis/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
 2007-12-14 21:05:09 UTC (rev 7182)
+++ 
gnuradio/branches/developers/gnychis/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
 2007-12-14 22:04:34 UTC (rev 7183)
@@ -61,10 +61,13 @@
     // USB side fifo
     wire [11:0] rdusedw;
     wire [11:0] wrusedw;
-    wire [15:0] fifodata;
+       wire [15:0] fifodata;
+       reg [15:0] fifodata_16;
     wire WR;
     wire have_space;
 
+       assign fifodata = fifodata_16;
+
     fifo_4kx16_dc      rx_usb_fifo (
             .aclr ( reset ),
             .data ( fifodata ),
@@ -120,9 +123,9 @@
         // TODO write this genericly
         wire [15:0]ch[NUM_CHAN:0];
         assign ch[0] = ch_0;
-        
+       
         wire cmd_empty;
-
+       
     always @(posedge rxclk)
         if(reset)
             rx_WR_enabled <= 1;
@@ -131,6 +134,31 @@
         else if(rx_WR_done)
             rx_WR_enabled <= 0;
 
+       // Switching of channels
+       reg [3:0] store_next;
+       always @(posedge rxclk)
+               if(reset)
+                       store_next <= #1 4'd0;
+               else if(rxstrobe & (store_next == 0))
+                       store_next <= #1 4'd1;
+               else if(~rx_full & (store_next == channels))
+                       store_next <= #1 4'd0;
+               else if(~rx_full & (store_next != 0))
+                       store_next <= #1 store_next + 4'd1;
+                       
+       always @*
+               case(store_next)
+                       4'd1 : fifodata_16 = ch_0;
+                       4'd2 : fifodata_16 = ch_1;
+                       4'd3 : fifodata_16 = ch_2;
+                       4'd4 : fifodata_16 = ch_3;
+                       4'd5 : fifodata_16 = ch_4;
+                       4'd6 : fifodata_16 = ch_5;
+                       4'd7 : fifodata_16 = ch_6;
+                       4'd8 : fifodata_16 = ch_7;
+                       default: fifodata_16 = 16'hFFFF;
+               endcase
+
        wire [15:0] dataout [0:NUM_CHAN];
        wire [9:0]  usedw       [0:NUM_CHAN];
        wire empty[0:NUM_CHAN];
@@ -145,7 +173,7 @@
        fifo_1kx16 rx_chan_fifo (
                 .aclr ( reset ),
                 .clock ( rxclk ),
-                .data ( ch[i] ),
+                .data ( fifodata ),
                 .rdreq ( rdreq ),
              .wrreq ( ~rx_full[i] & rxstrobe),
                 .empty (empty[i]),