[Commit-gnuradio] r7191 - in usrp2/trunk/firmware: apps lib

[eb]

Author: eb
Date: 2007-12-15 00:37:56 -0700 (Sat, 15 Dec 2007)
New Revision: 7191

Modified:
   usrp2/trunk/firmware/apps/tx_standalone.c
   usrp2/trunk/firmware/lib/ad9777_regs.h
   usrp2/trunk/firmware/lib/u2_init.c
Log:
Tx DAC now running at 400 MS/s ;)


Modified: usrp2/trunk/firmware/apps/tx_standalone.c
===================================================================
--- usrp2/trunk/firmware/apps/tx_standalone.c   2007-12-15 07:03:04 UTC (rev 
7190)
+++ usrp2/trunk/firmware/apps/tx_standalone.c   2007-12-15 07:37:56 UTC (rev 
7191)
@@ -251,8 +251,7 @@
   //pkt.ehdr.dst = *host;
   pkt.ehdr.ethertype = U2_ETHERTYPE;
   u2p_set_word0(&pkt.fixed,
-               U2P_TX_IMMEDIATE | U2P_TX_START_OF_BURST | U2P_TX_END_OF_BURST,
-               0);
+               U2P_TX_IMMEDIATE | U2P_TX_START_OF_BURST, 0);
   u2p_set_timestamp(&pkt.fixed, T_NOW);
 
   memcpy_wordaligned(buffer_ram(DSP_TX_BUF_0), &pkt, sizeof(pkt));
@@ -263,7 +262,7 @@
 
   // setup Tx DSP regs
   dsp_tx_regs->clear_state = 1;                        // reset
-  dsp_tx_regs->freq = 429496729;       // 10MHz [2**32 * fc/fsample]
+  dsp_tx_regs->freq = 408021893;               // 9.5 MHz [2**32 * fc/fsample]
   dsp_tx_regs->scale_iq = (tx_scale << 16) | tx_scale;
   dsp_tx_regs->interp_rate = 31;               // register gets N - 1
 

Modified: usrp2/trunk/firmware/lib/ad9777_regs.h
===================================================================
--- usrp2/trunk/firmware/lib/ad9777_regs.h      2007-12-15 07:03:04 UTC (rev 
7190)
+++ usrp2/trunk/firmware/lib/ad9777_regs.h      2007-12-15 07:37:56 UTC (rev 
7191)
@@ -23,7 +23,7 @@
 #define        R0_POWER_DN     (1 << 3)
 #define        R0_1R           (1 << 2)
 #define R0_2R          (0 << 2)
-#define        RO_PLL_LOCKED   (1 << 1)
+#define        R0_PLL_LOCKED   (1 << 1)
 
 #define        R1_INTERP_1X    0x00
 #define        R1_INTERP_2X    0x40
@@ -40,7 +40,7 @@
 #define        R1_NEG_EXP      (0 << 1)        // exp(-jwt)
 #define        R1_DATACLK_OUT  (1 << 0)
 
-#define        R2_2S_COMP      (1 << 7)
+#define        R2_2S_COMP      (0 << 7)
 #define R2_2PORT_MODE  (0 << 6)
 #define        R2_1PORT_MODE   (1 << 6)
 

Modified: usrp2/trunk/firmware/lib/u2_init.c
===================================================================
--- usrp2/trunk/firmware/lib/u2_init.c  2007-12-15 07:03:04 UTC (rev 7190)
+++ usrp2/trunk/firmware/lib/u2_init.c  2007-12-15 07:37:56 UTC (rev 7191)
@@ -74,10 +74,10 @@
   //spi_transact(SPI_TXONLY, SPI_SS_AD9777, 0x00000480, 16, 0);  // PLL on, 
automatic
 
   ad9777_write_reg(0, R0_1R);
-  ad9777_write_reg(1, R1_INTERP_1X | R1_REAL_MIX);
+  ad9777_write_reg(1, R1_INTERP_4X | R1_REAL_MIX);
   ad9777_write_reg(2, 0);
-  ad9777_write_reg(3, 0);
-  ad9777_write_reg(4, 0);
+  ad9777_write_reg(3, R3_PLL_DIV_1);
+  ad9777_write_reg(4, R4_PLL_ON | R4_CP_AUTO);
   ad9777_write_reg(5, R5_I_FINE_GAIN(0));
   ad9777_write_reg(6, R6_I_COARSE_GAIN(0xf));
   ad9777_write_reg(7, 0);      // I dac offset
@@ -104,6 +104,10 @@
   hal_set_leds(0x0, 0x3);
   mdelay(100);
 
+  int r0 = ad9777_read_reg(r0);
+  if (r0 & R0_PLL_LOCKED)
+    hal_set_leds(0x2, 0x2);
+  
   return true;
 }