[Commit-gnuradio] r7175 - in usrp2/trunk/fpga: control_lib eth sdr_lib serdes

[matt]

Author: matt
Date: 2007-12-14 01:59:31 -0700 (Fri, 14 Dec 2007)
New Revision: 7175

Modified:
   usrp2/trunk/fpga/control_lib/cascadefifo.v
   usrp2/trunk/fpga/control_lib/cascadefifo2.v
   usrp2/trunk/fpga/control_lib/longfifo.v
   usrp2/trunk/fpga/control_lib/shortfifo.v
   usrp2/trunk/fpga/eth/mac_txfifo_int.v
   usrp2/trunk/fpga/sdr_lib/rx_control.v
   usrp2/trunk/fpga/sdr_lib/tx_control.v
   usrp2/trunk/fpga/serdes/serdes_rx.v
   usrp2/trunk/fpga/serdes/serdes_tx.v
Log:
clearable fifos


Modified: usrp2/trunk/fpga/control_lib/cascadefifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/cascadefifo.v  2007-12-14 08:56:50 UTC (rev 
7174)
+++ usrp2/trunk/fpga/control_lib/cascadefifo.v  2007-12-14 08:59:31 UTC (rev 
7175)
@@ -16,6 +16,7 @@
      output [WIDTH-1:0] dataout,
      input read,
      input write,
+     input clear,
      output full,
      output empty,
      output [15:0] fifo_space);
@@ -24,12 +25,12 @@
    wire            empty_int, full_int, transfer;
    
    shortfifo #(.WIDTH(WIDTH)) shortfifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(clear),
       .datain(datain), .write(write), .full(full),
       .dataout(data_int), .read(transfer), .empty(empty_int) );
 
    longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(clear),
       .datain(data_int), .write(transfer), .full(full_int),
       .dataout(dataout), .read(read), .empty(empty),
       .fifo_space(fifo_space) );

Modified: usrp2/trunk/fpga/control_lib/cascadefifo2.v
===================================================================
--- usrp2/trunk/fpga/control_lib/cascadefifo2.v 2007-12-14 08:56:50 UTC (rev 
7174)
+++ usrp2/trunk/fpga/control_lib/cascadefifo2.v 2007-12-14 08:59:31 UTC (rev 
7175)
@@ -13,6 +13,7 @@
      output [WIDTH-1:0] dataout,
      input read,
      input write,
+     input clear,
      output full,
      output empty,
      output [15:0] fifo_space);
@@ -22,18 +23,18 @@
    wire            empty_int2, full_int2, transfer2;
    
    shortfifo #(.WIDTH(WIDTH)) shortfifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(clear),
       .datain(datain), .write(write), .full(full),
       .dataout(data_int), .read(transfer), .empty(empty_int) );
 
    longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(clear),
       .datain(data_int), .write(transfer), .full(full_int),
       .dataout(data_int2), .read(transfer2), .empty(empty_int2),
       .fifo_space(fifo_space) );
 
    shortfifo #(.WIDTH(WIDTH)) shortfifo2
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(clear),
       .datain(data_int2), .write(transfer2), .full(full_int2),
       .dataout(dataout), .read(read), .empty(empty) );
 

Modified: usrp2/trunk/fpga/control_lib/longfifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/longfifo.v     2007-12-14 08:56:50 UTC (rev 
7174)
+++ usrp2/trunk/fpga/control_lib/longfifo.v     2007-12-14 08:59:31 UTC (rev 
7175)
@@ -12,6 +12,7 @@
      output [WIDTH-1:0] dataout,
      input read,
      input write,
+     input clear,
      output full,
      output empty,
      output [15:0] fifo_space);
@@ -58,38 +59,46 @@
          empty_reg <= 1;
        end
      else
-       case(read_state)
-        EMPTY :
-          if(write)
+       if(clear)
+        begin
+           read_state <= EMPTY;
+           rd_addr <= 0;
+           empty_reg <= 1;
+        end
+       else 
+        case(read_state)
+          EMPTY :
+            if(write)
+              begin
+                 //rd_addr <= wr_addr;
+                 read_state <= PRE_READ;
+              end
+          PRE_READ :
             begin
-               //rd_addr <= wr_addr;
-               read_state <= PRE_READ;
+               read_state <= READING;
+               empty_reg <= 0;
+               rd_addr <= rd_addr + 1;
             end
-        PRE_READ :
-          begin
-             read_state <= READING;
-             empty_reg <= 0;
-             rd_addr <= rd_addr + 1;
-          end
-        
-        READING :
-          if(read)
-            if(rd_addr == wr_addr)
-              begin
-                 empty_reg <= 1;
-                 if(write)
-                   read_state <= PRE_READ;
-                 else
-                   read_state <= EMPTY;
-              end
-            else
-              rd_addr <= rd_addr + 1;
-
-       endcase // case(read_state)
-
+          
+          READING :
+            if(read)
+              if(rd_addr == wr_addr)
+                begin
+                   empty_reg <= 1;
+                   if(write)
+                     read_state <= PRE_READ;
+                   else
+                     read_state <= EMPTY;
+                end
+              else
+                rd_addr <= rd_addr + 1;
+        endcase // case(read_state)
+   
    always @(posedge clk)
      if(rst)
        full_reg <= 0;
+     else if(clear)
+       full_reg <= 0;
      else if(read & ~write)
        full_reg <= 0;
      else if(write & ~read & (wr_addr == (rd_addr-3)))

Modified: usrp2/trunk/fpga/control_lib/shortfifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/shortfifo.v    2007-12-14 08:56:50 UTC (rev 
7174)
+++ usrp2/trunk/fpga/control_lib/shortfifo.v    2007-12-14 08:59:31 UTC (rev 
7175)
@@ -6,6 +6,7 @@
      output [WIDTH-1:0] dataout,
      input read,
      input write,
+     input clear,
      output reg full,
      output reg empty);
    
@@ -29,6 +30,12 @@
          empty <= 1;
          full <= 0;
        end
+     else if(clear)
+       begin
+         a <= 0;
+         empty <= 1;
+         full<= 0;
+       end
      else if(read & ~write)
        begin
          full <= 0;
@@ -46,8 +53,6 @@
            full <= 1;
        end
 
-   //   assign full = (a == 15);
-
    // NOTE will fail if you write into a full fifo or read from an empty one
 
 endmodule // shortfifo

Modified: usrp2/trunk/fpga/eth/mac_txfifo_int.v
===================================================================
--- usrp2/trunk/fpga/eth/mac_txfifo_int.v       2007-12-14 08:56:50 UTC (rev 
7174)
+++ usrp2/trunk/fpga/eth/mac_txfifo_int.v       2007-12-14 08:59:31 UTC (rev 
7175)
@@ -24,7 +24,7 @@
    wire [33:0] sfifo_in, sfifo_out;
    
    shortfifo #(.WIDTH(34)) txmac_sfifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(0),
       .datain(sfifo_in),.write(sfifo_write),.full(full),
       .dataout(sfifo_out),.read(sfifo_read),.empty(empty));
    

Modified: usrp2/trunk/fpga/sdr_lib/rx_control.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/rx_control.v       2007-12-14 08:56:50 UTC (rev 
7174)
+++ usrp2/trunk/fpga/sdr_lib/rx_control.v       2007-12-14 08:59:31 UTC (rev 
7175)
@@ -21,7 +21,10 @@
      // From DSP Core
      input [31:0] sample,
      output run,
-     input strobe
+     input strobe,
+
+     // Debug
+     output [31:0] debug_rx
      );
 
    wire [31:0] new_time, new_command;
@@ -50,7 +53,7 @@
    wire        full_ctrl, read_ctrl, empty_ctrl;
 
    shortfifo #(.WIDTH(64)) commandfifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(clear_overrun),
       .datain({new_time,new_command}), .write(store_command), .full(full_ctrl),
       .dataout({rcvtime_pre,numlines,lines_per_frame}), .read(read_ctrl), 
.empty(empty_ctrl) );
 
@@ -87,7 +90,7 @@
    wire [33:0] fifo_line;
    // Internal FIFO, size 9 is 2K, size 10 is 4K
    cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) rxfifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(clear_overrun),
       .datain(fifo_line), .write(write), .full(full),
       .dataout({sop_o,eop_o,wr_dat_o}), .read(read), .empty(empty)
       );
@@ -161,5 +164,6 @@
    assign  overrun = (ibs_state == IBS_OVERRUN);
    assign  run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE);
    assign  read_ctrl = (ibs_state == IBS_IDLE) & ~empty_ctrl;
- 
+
+   assign  debug_rx = {24'd0, sc_pre1, clear_overrun, go_now, too_late, 
overrun, ibs_state[2:0] };
 endmodule // rx_control

Modified: usrp2/trunk/fpga/sdr_lib/tx_control.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/tx_control.v       2007-12-14 08:56:50 UTC (rev 
7174)
+++ usrp2/trunk/fpga/sdr_lib/tx_control.v       2007-12-14 08:59:31 UTC (rev 
7175)
@@ -68,12 +68,12 @@
    wire [31:0] sendtime;
    
    cascadefifo #(.WIDTH(34),.SIZE(FIFOSIZE)) txfifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(clear_state),
       .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write_data), 
.full(full_data),
       .dataout({sop_o,eop_o,data_o}), .read(read_data), .empty(empty_data) );
 
    shortfifo #(.WIDTH(35)) ctrlfifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(clear_state),
       .datain({held_flags[2:0],rd_dat_i}), .write(write_ctrl), 
.full(full_ctrl),
       .dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl), 
.empty(empty_ctrl) );
 

Modified: usrp2/trunk/fpga/serdes/serdes_rx.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes_rx.v 2007-12-14 08:56:50 UTC (rev 7174)
+++ usrp2/trunk/fpga/serdes/serdes_rx.v 2007-12-14 08:59:31 UTC (rev 7175)
@@ -244,7 +244,7 @@
    // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes
    assign write = eop_i | (error_i & ~full) | (write_d & (state != CRC_CHECK));
    cascadefifo2 #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(0),
       .datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full),
       .dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty),
       .fifo_space(fifo_space) );

Modified: usrp2/trunk/fpga/serdes/serdes_tx.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes_tx.v 2007-12-14 08:56:50 UTC (rev 7174)
+++ usrp2/trunk/fpga/serdes/serdes_tx.v 2007-12-14 08:59:31 UTC (rev 7175)
@@ -76,7 +76,7 @@
    reg                xfer_active;
    
    cascadefifo #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
-     (.clk(clk),.rst(rst),
+     (.clk(clk),.rst(rst),.clear(0),
       .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full),
       .dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty) );