[Commit-gnuradio] r7173 - usrp2/trunk/fpga/top/u2_basic

[matt]

Author: matt
Date: 2007-12-14 01:24:26 -0700 (Fri, 14 Dec 2007)
New Revision: 7173

Modified:
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
add some debugging, invert sense of adc enables, temporarily reduce size of 
fifo on eth receive


Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-12-14 08:23:00 UTC (rev 
7172)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-12-14 08:24:26 UTC (rev 
7173)
@@ -72,13 +72,13 @@
    // ADC
    input [13:0] adc_a,
    input adc_ovf_a,
-   output adc_oen_a,
-   output adc_pdn_a,
+   output adc_on_a,
+   output adc_oe_a,
    
    input [13:0] adc_b,
    input adc_ovf_b,
-   output adc_oen_b,
-   output adc_pdn_b,
+   output adc_on_b,
+   output adc_oe_b,
    
    // DAC
    output [15:0] dac_a,
@@ -134,6 +134,7 @@
    wire        bus_error, spi_int, i2c_int, timer_int, buffer_int, proc_int, 
overrun, underrun, uart_int;
 
    wire [31:0]         debug_gpio_0, debug_gpio_1;
+   wire [31:0]         debug_rx, debug_rx_1, debug_rx_2;
    wire [31:0]         debug_wb, debug_txmacfifo_in, debug_txmacfifo_out, 
debug_bufpool, debug_bufpool2;
    wire [15:0]         debug_gmii_1, debug_gmii_2;
    wire [31:0]         atr_lines;
@@ -371,7 +372,7 @@
    wire [7:0]   clock_outs, serdes_outs, adc_outs, misc_outs;
    assign       {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
    assign       {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = 
serdes_outs[3:0];
-   assign       {adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0];
+   assign       {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
    assign       {led2, led1} = misc_outs[1:0];
 
    wire         phy_reset;
@@ -396,7 +397,7 @@
    wire [31:0]          Tx_mac_data, Rx_mac_data;
    wire [1:0]   Tx_mac_BE, Rx_mac_BE;
 
-   MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11))
+   MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(10))
      MAC_top
        (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),.Speed(),
        
.RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
@@ -508,7 +509,8 @@
       .master_time(master_time),.overrun(overrun),
       .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), 
.wr_error_o(wr1_error),
       .wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
-      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx) );
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .debug_rx(debug_rx) );
    
    dsp_core_rx dsp_core_rx
      (.clk(dsp_clk),.rst(dsp_rst),
@@ -547,40 +549,16 @@
    // 
/////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
 
-   wire [31:0] debug_cpld = 
{{ram_loader_we,ram_loader_done,clock_ready,ram_loader_ack,ram_loader_stb,ram_loader_rst,wb_rst,dsp_rst},
-                            {ram_loader_done ? {2'b00, iwb_adr[13:0]} : 
{2'b00,ram_loader_adr[13:0]}},
-                            
{proc_int,timer_int,cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached}
 };
-   
-   wire [31:0] debug_new = {{ram_loader_done ? {2'b00, iwb_adr[13:0]} : 
{2'b00, ram_loader_adr[13:0]}},
-                           {3'b0,ram_loader_done,clock_ready, wb_rst, 
proc_int,timer_int},
-                           {1'b0, 
GMII_TX_CLK,clk_to_mac,PHY_CLK,MDC,MDIO,PHY_INTn,PHY_RESETn} };
-   
-   wire [31:0] debug_iram_dat = ram_loader_done ? iwb_dat : ram_loader_dat;
-   
-   assign      debug_wb = {m0_adr[15:0], m0_sel[3:0], m0_ack, m0_we, m0_stb, 
m0_err};
-   
-   reg [13:0]  debug_gmii_1_reg, debug_gmii_2_reg;
-   
-   always @(posedge GMII_GTX_CLK)
-     debug_gmii_1_reg <=  
{GMII_COL,GMII_CRS,GMII_RX_DV,GMII_RX_ER,GMII_TX_EN,GMII_TX_ER,GMII_TXD[7:0]};
-   always @(posedge GMII_RX_CLK)
-     debug_gmii_2_reg <= 
{GMII_COL,GMII_CRS,GMII_RX_DV,GMII_RX_ER,GMII_TX_EN,GMII_TX_ER,GMII_RXD[7:0]};
-   
-   assign      debug_gmii_1 = {GMII_GTX_CLK,GMII_TX_CLK,debug_gmii_1_reg};
-   assign      debug_gmii_2 = {GMII_RX_CLK,1'b0,debug_gmii_2_reg};
-   
-   assign      debug_txmacfifo_out = {Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, 
Tx_mac_eop, uart_tx_o, Tx_mac_data[26:0]};
-   assign      debug_txmacfifo_in = {rd2_read, rd2_done, rd2_sop, rd2_eop, 
rd2_error, rd2_dat[26:0]};
-   
-   assign      debug_bufpool = {uart_baud_o,uart_tx_o,  GMII_TX_EN,GMII_TX_ER,
-                               PHY_INTn,buffer_int,timer_int,proc_int,
-                               GMII_TXD[7:0], status[15:0]  };
-   
-   assign      debug = debug_bufpool;
+   assign      debug_rx_1 = 
{uart_tx_o,run_rx,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
+                            GMII_RXD,
+                            adc_ovf_a_reg1, adc_ovf_b_reg1, adc_a_reg1};
+   assign      debug_rx_2 = { sample_rx[31:16], 8'd0, debug_rx[7:0] };
+
+   assign      debug = debug_rx_2;
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
 
-   assign      debug_gpio_0 = debug_bufpool;
-   assign      debug_gpio_1 = debug_txmacfifo_out;
+   assign      debug_gpio_0 = 32'd0;
+   assign      debug_gpio_1 = debug_rx_1;
    
 endmodule // u2_basic