[Commit-gnuradio] r7145 - in usrp2/trunk/fpga/top: u2_basic u2_fpga

[matt]

Author: matt
Date: 2007-12-12 22:10:13 -0700 (Wed, 12 Dec 2007)
New Revision: 7145

Modified:
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
Log:
extend the length of the eth rx fifo, add uart output to the debug pins


Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-12-13 05:06:37 UTC (rev 
7144)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-12-13 05:10:13 UTC (rev 
7145)
@@ -396,7 +396,7 @@
    wire [31:0]          Tx_mac_data, Rx_mac_data;
    wire [1:0]   Tx_mac_BE, Rx_mac_BE;
 
-   MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(9))
+   MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11))
      MAC_top
        (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),.Speed(),
        
.RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
@@ -569,22 +569,18 @@
    assign      debug_gmii_1 = {GMII_GTX_CLK,GMII_TX_CLK,debug_gmii_1_reg};
    assign      debug_gmii_2 = {GMII_RX_CLK,1'b0,debug_gmii_2_reg};
    
-   assign      debug_txmacfifo_out = {Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, 
Tx_mac_eop, 1'b0, Tx_mac_data[26:0]};
+   assign      debug_txmacfifo_out = {Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, 
Tx_mac_eop, uart_tx_o, Tx_mac_data[26:0]};
    assign      debug_txmacfifo_in = {rd2_read, rd2_done, rd2_sop, rd2_eop, 
rd2_error, rd2_dat[26:0]};
    
    assign      debug_bufpool = {uart_baud_o,uart_tx_o,  GMII_TX_EN,GMII_TX_ER,
                                PHY_INTn,buffer_int,timer_int,proc_int,
                                GMII_TXD[7:0], status[15:0]  };
    
-   assign      debug_bufpool2 = { led1,led2,iwb_adr[13:0],
-                                 Tx_mac_wa, Tx_mac_wr,rd2_read,rd2_done,
-                                 rd2_error,rd2_sop,rd2_eop,status_b0[8:0]  };
-   
-   assign      debug = debug_bufpool2;
+   assign      debug = debug_bufpool;
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
 
    assign      debug_gpio_0 = debug_bufpool;
-   assign      debug_gpio_1 = debug_txmacfifo_in;
+   assign      debug_gpio_1 = debug_txmacfifo_out;
    
 endmodule // u2_basic

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)