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[Commit-gnuradio] r7140 - usrp2/trunk/fpga/control_lib


From: eb
Subject: [Commit-gnuradio] r7140 - usrp2/trunk/fpga/control_lib
Date: Wed, 12 Dec 2007 20:34:22 -0700 (MST)

Author: eb
Date: 2007-12-12 20:34:21 -0700 (Wed, 12 Dec 2007)
New Revision: 7140

Modified:
   usrp2/trunk/fpga/control_lib/buffer_pool.v
Log:
Reverted accidental checkin.  Reverse merged 7139:7138


Modified: usrp2/trunk/fpga/control_lib/buffer_pool.v
===================================================================
--- usrp2/trunk/fpga/control_lib/buffer_pool.v  2007-12-13 01:41:45 UTC (rev 
7139)
+++ usrp2/trunk/fpga/control_lib/buffer_pool.v  2007-12-13 03:34:21 UTC (rev 
7140)
@@ -63,6 +63,7 @@
    
    wire [7:0]   done;
    wire [7:0]   error;
+   wire [7:0]   idle;
    
    wire [31:0]          buf_doa[0:7];
    
@@ -86,7 +87,7 @@
    wire [7:0]   rd_sop_o;
    wire [7:0]   rd_eop_o;
    
-   assign       status = {16'd0,error[7:0],done[7:0]};
+   assign       status = {8'd0,idle[7:0],error[7:0],done[7:0]};
 
    assign       s0 = {23'd0,buf_addrb[0]};
    assign       s1 = {23'd0,buf_addrb[1]};
@@ -133,18 +134,11 @@
    generate
       for(i=0;i<8;i=i+1)
        begin : gen_buffer
-          RAMB16_S36_S36 dpram
-            
(.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0),
-             .ENA(wb_stb_i & sel_a[i]),.SSRA(),.WEA(wb_we_i),
-             
.DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0),
-             .ENB(buf_enb[i]),.SSRB(),.WEB(buf_web[i]) );
-          
-          /* ram_2port #(.DWIDTH(32),.AWIDTH(9)) buffer
+          ram_2port #(.DWIDTH(32),.AWIDTH(9)) buffer
             (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i),
              .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
              .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),
-             .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); */
-
+             .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); 
           buffer_int #(.BUFF_NUM(i)) fifo_int
             (.clk(stream_clk),.rst(stream_rst),
              .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)),





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