[Commit-gnuradio] r7131 - in usrp2/trunk/fpga/eth/rtl/verilog: . MAC_rx

[matt]

Author: matt
Date: 2007-12-12 13:43:32 -0700 (Wed, 12 Dec 2007)
New Revision: 7131

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
   usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v
Log:
clean up logic for synthesis


Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2007-12-12 20:25:07 UTC 
(rev 7130)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2007-12-12 20:43:32 UTC 
(rev 7131)
@@ -87,7 +87,7 @@
      output [31:0] Rx_mac_data,
      output [1:0]  Rx_mac_BE,
      output reg    Rx_mac_pa,
-     output        Rx_mac_sop,
+     output reg    Rx_mac_sop,
      output        Rx_mac_err,
      output        Rx_mac_eop );
    
@@ -163,7 +163,6 @@
   reg       Fifo_data_en_dl1;
   reg [7:0] Fifo_data_dl1;
   reg       Rx_mac_sop_tmp;
-  reg       Rx_mac_sop;
 
   reg [2:0] Next_state_SYS;
   reg       Packet_number_sub;

Modified: usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v     2007-12-12 20:25:07 UTC 
(rev 7130)
+++ usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v     2007-12-12 20:43:32 UTC 
(rev 7131)
@@ -42,7 +42,6 @@
        begin
          xon_int <= 0;
          xoff_int <= 0;
-         countdown <= 0;
        end
      else 
        begin