[Commit-gnuradio] r7118 - in usrp2/trunk/firmware: apps lib

[eb]

Author: eb
Date: 2007-12-11 20:53:30 -0700 (Tue, 11 Dec 2007)
New Revision: 7118

Modified:
   usrp2/trunk/firmware/apps/ibs_rx_test.c
   usrp2/trunk/firmware/apps/ibs_tx_test.c
   usrp2/trunk/firmware/apps/test1.c
   usrp2/trunk/firmware/lib/memory_map.h
Log:
Changed entries in memory_map.h to use explict width ints.
Changed 16-bit scale_i, scale_q to 32-bit scale_iq.


Modified: usrp2/trunk/firmware/apps/ibs_rx_test.c
===================================================================
--- usrp2/trunk/firmware/apps/ibs_rx_test.c     2007-12-12 03:51:45 UTC (rev 
7117)
+++ usrp2/trunk/firmware/apps/ibs_rx_test.c     2007-12-12 03:53:30 UTC (rev 
7118)
@@ -28,8 +28,7 @@
   output_regs->adc_ctrl = 0x0A;
 
   dsp_rx_regs->freq = 0;
-  dsp_rx_regs->scale_i = 1;
-  dsp_rx_regs->scale_q = 1;
+  dsp_rx_regs->scale_iq = (1 << 16) | 1;
   dsp_rx_regs->decim_rate = 7;
 
   volatile unsigned int *buffer0 = buffer_ram(0);

Modified: usrp2/trunk/firmware/apps/ibs_tx_test.c
===================================================================
--- usrp2/trunk/firmware/apps/ibs_tx_test.c     2007-12-12 03:51:45 UTC (rev 
7117)
+++ usrp2/trunk/firmware/apps/ibs_tx_test.c     2007-12-12 03:53:30 UTC (rev 
7118)
@@ -32,8 +32,7 @@
   u2_init();
   
   dsp_tx_regs->freq = 0;
-  dsp_tx_regs->scale_i = 1;
-  dsp_tx_regs->scale_q = 1;
+  dsp_tx_regs->scale_iq = (1 << 16) | 1;
   dsp_tx_regs->interp_rate = 7;
 
   // Write data to be sent into the first buffer

Modified: usrp2/trunk/firmware/apps/test1.c
===================================================================
--- usrp2/trunk/firmware/apps/test1.c   2007-12-12 03:51:45 UTC (rev 7117)
+++ usrp2/trunk/firmware/apps/test1.c   2007-12-12 03:53:30 UTC (rev 7118)
@@ -46,14 +46,12 @@
 
   // Set up TX Chain
   dsp_tx_regs->freq = 0;
-  dsp_tx_regs->scale_i = 1;
-  dsp_tx_regs->scale_q = 1;
+  dsp_tx_regs->scale_iq = (1 << 16) | 1;
   dsp_tx_regs->interp_rate = 7;
 
   // Set up RX Chain
   dsp_rx_regs->freq = 0;
-  dsp_rx_regs->scale_i = 1;
-  dsp_rx_regs->scale_q = 1;
+  dsp_rx_regs->scale_iq = (1 << 16) | 1;
   dsp_rx_regs->decim_rate = 7;
 
   // Set up buffer control, using only 4 for now

Modified: usrp2/trunk/firmware/lib/memory_map.h
===================================================================
--- usrp2/trunk/firmware/lib/memory_map.h       2007-12-12 03:51:45 UTC (rev 
7117)
+++ usrp2/trunk/firmware/lib/memory_map.h       2007-12-12 03:53:30 UTC (rev 
7118)
@@ -19,6 +19,9 @@
 #ifndef INCLUDED_MEMORY_MAP_H
 #define INCLUDED_MEMORY_MAP_H
 
+#include <stdint.h>
+
+
 #define MASTER_CLK_RATE        100000000               // 100 MHz
 
 
@@ -47,7 +50,7 @@
 #define BUFFER_POOL_BUFFER_SIZE 0x0200  // Buffer size in 32-bit lines
 
 #define buffer_pool_ram \
-  ((volatile unsigned int *) BUFFER_POOL_RAM_BASE)
+  ((volatile uint32_t *) BUFFER_POOL_RAM_BASE)
 
 #define buffer_ram(n) (&buffer_pool_ram[(n) * BUFFER_POOL_BUFFER_SIZE])
 
@@ -94,11 +97,11 @@
 #define I2C_BASE 0x9000
 
 typedef struct {
-  volatile unsigned int  prescaler_lo; // r/w
-  volatile unsigned int  prescaler_hi; // r/w
-  volatile unsigned int  ctrl;         // r/w
-  volatile unsigned int  data;         // wr = transmit reg; rd = receive reg
-  volatile unsigned int  cmd_status;   // wr = command reg;  rd = status reg
+  volatile uint32_t  prescaler_lo;     // r/w
+  volatile uint32_t  prescaler_hi;     // r/w
+  volatile uint32_t  ctrl;             // r/w
+  volatile uint32_t  data;             // wr = transmit reg; rd = receive reg
+  volatile uint32_t  cmd_status;       // wr = command reg;  rd = status reg
 } i2c_regs_t;
 
 #define i2c_regs ((i2c_regs_t *) I2C_BASE)
@@ -136,9 +139,9 @@
 #define GPIO_BASE 0xA000
 
 typedef struct {
-  volatile unsigned int                io;       // tx data in high 16, rx in 
low 16
-  volatile unsigned int                rx_mode;  // 16 2-bit fields
-  volatile unsigned int                tx_mode;  // 16 2-bit fields
+  volatile uint32_t    io;       // tx data in high 16, rx in low 16
+  volatile uint32_t    rx_mode;  // 16 2-bit fields
+  volatile uint32_t    tx_mode;  // 16 2-bit fields
 } gpio_regs_t;
 
 // each 2-bit mode field is layed out this way
@@ -159,9 +162,9 @@
 #define BUFFER_POOL_STATUS_BASE 0xB000
 
 typedef struct {
-  volatile unsigned last_line[8];     // last line xfer'd in buffer
-  volatile unsigned status;          // error and done flags
-  volatile unsigned hw_config;       // see below
+  volatile uint32_t last_line[8];     // last line xfer'd in buffer
+  volatile uint32_t status;          // error and done flags
+  volatile uint32_t hw_config;       // see below
 } buffer_pool_status_t;
 
 #define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE)
@@ -233,7 +236,7 @@
 // --- buffer pool control regs ---
 
 typedef struct {
-  volatile unsigned int ctrl;
+  volatile uint32_t ctrl;
 } buffer_pool_ctrl_t;
 
 // buffer pool ports
@@ -281,11 +284,11 @@
 // --- misc outputs ---
 
 typedef struct {
-  volatile unsigned long       clk_ctrl;
-  volatile unsigned long       serdes_ctrl;
-  volatile unsigned long       adc_ctrl;
-  volatile unsigned long       leds;
-  volatile unsigned long       phy_ctrl;       // LSB is reset line to eth phy
+  volatile uint32_t    clk_ctrl;
+  volatile uint32_t    serdes_ctrl;
+  volatile uint32_t    adc_ctrl;
+  volatile uint32_t    leds;
+  volatile uint32_t    phy_ctrl;       // LSB is reset line to eth phy
 } output_regs_t;
 
 #define SERDES_ENABLE 8
@@ -298,11 +301,10 @@
 // --- dsp tx regs ---
 
 typedef struct {
-  volatile int         freq;
-  volatile short       scale_i;
-  volatile short       scale_q;
-  volatile int          interp_rate;
-  volatile int          clear_state;
+  volatile int32_t     freq;
+  volatile uint32_t    scale_iq;       // {scale_i,scale_q}
+  volatile uint32_t     interp_rate;
+  volatile uint32_t     clear_state;
 } dsp_tx_regs_t;
   
 #define dsp_tx_regs ((dsp_tx_regs_t *) DSP_TX_BASE)
@@ -310,13 +312,12 @@
 // --- dsp rx regs ---
 
 typedef struct {
-  volatile int         freq;
-  volatile short       scale_i;
-  volatile short       scale_q;
-  volatile int          decim_rate;
-  volatile int          rx_time;
-  volatile int          rx_command;
-  volatile int          clear_state;
+  volatile int32_t     freq;
+  volatile uint32_t    scale_iq;       // {scale_i,scale_q}
+  volatile uint32_t     decim_rate;
+  volatile uint32_t     rx_time;       // when to begin reception
+  volatile uint32_t     rx_command;    // {num_lines(23), lines_per_frame(9)
+  volatile uint32_t     clear_state;
 } dsp_rx_regs_t;
   
 #define dsp_rx_regs ((dsp_rx_regs_t *) DSP_RX_BASE)
@@ -351,10 +352,10 @@
 
 
 typedef struct {
-  volatile int edge_enable;    // mask: 1 -> edge triggered, 0 -> level
-  volatile int polarity;       // mask: 1 -> rising edge
-  volatile int mask;           // mask: 1 -> disabled
-  volatile int pending;                // mask: 1 -> pending; write 1's to 
clear pending ints
+  volatile uint32_t edge_enable; // mask: 1 -> edge triggered, 0 -> level
+  volatile uint32_t polarity;   // mask: 1 -> rising edge
+  volatile uint32_t mask;       // mask: 1 -> disabled
+  volatile uint32_t pending;    // mask: 1 -> pending; write 1's to clear 
pending ints
 } pic_regs_t;
 
 #define pic_regs ((pic_regs_t *) PIC_BASE)
@@ -365,7 +366,7 @@
 #define TIMER_BASE  0xE800
 
 typedef struct {
-  volatile int time;   // R: current, W: set time to interrupt
+  volatile uint32_t time;      // R: current, W: set time to interrupt
 } timer_regs_t;
 
 #define timer_regs ((timer_regs_t *) TIMER_BASE)