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[Commit-gnuradio] r7109 - in gnuradio/branches/features/inband-usb/usrp/
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From: |
gnychis |
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Subject: |
[Commit-gnuradio] r7109 - in gnuradio/branches/features/inband-usb/usrp/fpga: inband_lib megacells rbf/rev2 rbf/rev4 toplevel/usrp_inband_usb toplevel/usrp_std |
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Date: |
Tue, 11 Dec 2007 15:34:32 -0700 (MST) |
Author: gnychis
Date: 2007-12-11 15:34:32 -0700 (Tue, 11 Dec 2007)
New Revision: 7109
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_demux.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16.bsf
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16.v
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16_bb.v
gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev2/std_inband.rbf
gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev4/std_inband.rbf
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
Log:
Merging -r6691:7108 from developers/zhuochen/inband
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-12-11 22:32:39 UTC (rev 7108)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-12-11 22:34:32 UTC (rev 7109)
@@ -21,7 +21,7 @@
input wire [31:0] rssi_wait;
output wire [14:0] debug;
- assign debug = {reader_state, trash, skip, timestamp[4:0], adc_time[4:0]};
+ assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe,
tx_clock};
// Should not be needed if adc clock rate < tx clock rate
// Used only to debug
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_demux.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_demux.v
2007-12-11 22:32:39 UTC (rev 7108)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_demux.v
2007-12-11 22:34:32 UTC (rev 7109)
@@ -1,24 +1,24 @@
module channel_demux
- #(parameter NUM_CHAN = 2, parameter CHAN_WIDTH = 2) ( //usb Side
- input [31:0]usbdata_final,
- input WR_final,
-
- // TX Side
- input reset,
- input txclk,
- output reg [CHAN_WIDTH:0] WR_channel,
- output reg [31:0] ram_data,
- output reg [CHAN_WIDTH:0] WR_done_channel );
-/* Parse header and forward to ram */
- reg [2:0]reader_state;
- reg [4:0]channel ;
- reg [6:0]read_length ;
+ #(parameter NUM_CHAN = 2) ( //usb Side
+ input [31:0]usbdata_final,
+ input WR_final,
+ // TX Side
+ input reset,
+ input txclk,
+ output reg [NUM_CHAN:0] WR_channel,
+ output reg [31:0] ram_data,
+ output reg [NUM_CHAN:0] WR_done_channel );
+ /* Parse header and forward to ram */
+ reg [2:0]reader_state;
+ reg [4:0]channel ;
+ reg [6:0]read_length ;
+
// States
- parameter IDLE = 3'd0;
- parameter HEADER = 3'd1;
- parameter WAIT = 3'd2;
- parameter FORWARD = 3'd3;
+ parameter IDLE = 3'd0;
+ parameter HEADER = 3'd1;
+ parameter WAIT = 3'd2;
+ parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
@@ -27,7 +27,7 @@
NUM_CHAN :
(usbdata_final[`CHANNEL]);
always @(posedge txclk)
- begin
+ begin
if (reset)
begin
reader_state <= IDLE;
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
2007-12-11 22:32:39 UTC (rev 7108)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
2007-12-11 22:34:32 UTC (rev 7109)
@@ -14,17 +14,17 @@
output reg WR,
output reg [15:0]fifodata,
input have_space,
- input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire
[31:0]rssi_2,
- input wire [31:0]rssi_3, output wire [7:0] debugbus,
- input [NUM_CHAN:0] underrun);
+ input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
+ input wire [31:0]rssi_3, output wire [7:0] debugbus,
+ input [NUM_CHAN:0] underrun);
// States
`define IDLE 3'd0
`define HEADER1 3'd1
- `define HEADER2 3'd2
+ `define HEADER2 3'd2
`define TIMESTAMP 3'd3
- `define FORWARD 3'd4
+ `define FORWARD 3'd4
`define MAXPAYLOAD 504
@@ -39,27 +39,32 @@
`define UNDERRUN 14
`define OVERRUN 15
- reg [NUM_CHAN:0] overrun;
+ reg [NUM_CHAN:0] overrun;
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
reg tstamp_complete;
reg [3:0] check_next;
- wire [8:0] chan_used;
+
wire [31:0] true_rssi;
- wire [4:0] true_channel;
+ wire [4:0] true_channel;
+ wire ready_to_send;
- assign debugbus = {state, chan_empty[0], underrun[0], check_next[0],
- have_space, rd_select[0]};
- assign chan_used = chan_usedw[8:0];
- assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
+ assign debugbus = {chan_empty[0], rd_select[0], have_space,
+ (chan_usedw >= 10'd504), (chan_usedw ==0),
+ ready_to_send, state[1:0]};
+
+ assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
((rd_select[0]) ?
rssi_1:rssi_0);
- assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next -
4'd1});
+ assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next -
4'd1});
+ assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
+ ((rd_select == NUM_CHAN)&&(chan_usedw > 0));
+
always @(posedge rxclk)
begin
if (reset)
begin
- overrun <= 0;
+ overrun <= 0;
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
@@ -69,32 +74,32 @@
end
else case (state)
`IDLE: begin
- chan_rdreq <= #1 0;
- //check if the channel is full
- if(~chan_empty[check_next])
- begin
- if (have_space)
- begin
- //transmit if the usb buffer
have space
- state <= #1 `HEADER1;
- overrun[check_next] <= 0;
- end
- else
- begin
- //wait if the usb buffer is
full and set overrun
- state <= #1 `IDLE;
- overrun[check_next] <= 1;
- end
- rd_select <= #1 check_next;
- end
- check_next <= #1 (check_next == channels ? 4'd0
: check_next + 4'd1);
+ chan_rdreq <= #1 0;
+ //check if the channel is full
+ if(~chan_empty[check_next])
+ begin
+ if (have_space)
+ begin
+ //transmit if the usb buffer have space
+ //check if we should send
+ if (ready_to_send)
+ state <= #1 `HEADER1;
+
+ overrun[check_next] <= 0;
+ end
+ else
+ begin
+ state <= #1 `IDLE;
+ overrun[check_next] <= 1;
+ end
+ rd_select <= #1 check_next;
+ end
+ check_next <= #1 (check_next == channels ? 4'd0 : check_next +
4'd1);
end
`HEADER1: begin
- fifodata[`PAYLOAD_LEN] <= #1 (chan_used > 9'd252
- ? 9'd252 : chan_used << 1);
- payload_len <= #1 (chan_used > 9'd252
- ? 9'd252 : chan_used << 1);
+ fifodata[`PAYLOAD_LEN] <= #1 9'd504;
+ payload_len <= #1 9'd504;
fifodata[`TAG] <= #1 0;
fifodata[`MBZ] <= #1 0;
WR <= #1 1;
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
2007-12-11 22:32:39 UTC (rev 7108)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
2007-12-11 22:34:32 UTC (rev 7109)
@@ -1,25 +1,57 @@
module register_io
- ( // System
- input clk, input reset, input wire [1:0] enable,
- input wire [6:0] addr, input wire [31:0] datain,
- output reg [31:0] dataout, output wire [15:0] debugbus,
- output reg [6:0] addr_wr, output reg [31:0] data_wr, output wire
strobe_wr,
- // output for rssi
- output wire [31:0] threshhold, output wire [31:0] rssi_wait,
- // Input data lines
- input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0]
rssi_2, input wire [31:0] rssi_3,
- input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0]
reg_2, input wire [15:0] reg_3,
- input wire [11:0] atr_tx_delay, input wire [11:0] atr_rx_delay, input
wire [7:0] master_controls,
- input wire [3:0] debug_en, input wire [7:0] interp_rate, input wire [7:0]
decim_rate,
- input wire [15:0] atr_mask_0, input wire [15:0] atr_txval_0, input wire
[15:0] atr_rxval_0,
- input wire [15:0] atr_mask_1, input wire [15:0] atr_txval_1, input wire
[15:0] atr_rxval_1,
- input wire [15:0] atr_mask_2, input wire [15:0] atr_txval_2, input wire
[15:0] atr_rxval_2,
- input wire [15:0] atr_mask_3, input wire [15:0] atr_txval_3, input wire
[15:0] atr_rxval_3,
- input wire [7:0] txa_refclk, input wire [7:0] txb_refclk, input wire
[7:0] rxa_refclk, input wire [7:0] rxb_refclk,
- input wire [7:0] misc, input wire [31:0] txmux);
-
- // assigning wires according to their address
- wire [31:0] bundle[43:0];
+ (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr,
strobe_wr,
+ rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1,
reg_2, reg_3,
+ atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate,
decim_rate,
+ atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1,
atr_rxval_1,
+ atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3,
atr_rxval_3,
+ txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);
+
+ input clk;
+ input reset;
+ input wire [1:0] enable;
+ input wire [6:0] addr;
+ input wire [31:0] datain;
+ output reg [31:0] dataout;
+ output wire [15:0] debugbus;
+ output reg [6:0] addr_wr;
+ output reg [31:0] data_wr;
+ output wire strobe_wr;
+ input wire [31:0] rssi_0;
+ input wire [31:0] rssi_1;
+ input wire [31:0] rssi_2;
+ input wire [31:0] rssi_3;
+ output wire [31:0] threshhold;
+ output wire [31:0] rssi_wait;
+ input wire [15:0] reg_0;
+ input wire [15:0] reg_1;
+ input wire [15:0] reg_2;
+ input wire [15:0] reg_3;
+ input wire [11:0] atr_tx_delay;
+ input wire [11:0] atr_rx_delay;
+ input wire [7:0] master_controls;
+ input wire [3:0] debug_en;
+ input wire [15:0] atr_mask_0;
+ input wire [15:0] atr_txval_0;
+ input wire [15:0] atr_rxval_0;
+ input wire [15:0] atr_mask_1;
+ input wire [15:0] atr_txval_1;
+ input wire [15:0] atr_rxval_1;
+ input wire [15:0] atr_mask_2;
+ input wire [15:0] atr_txval_2;
+ input wire [15:0] atr_rxval_2;
+ input wire [15:0] atr_mask_3;
+ input wire [15:0] atr_txval_3;
+ input wire [15:0] atr_rxval_3;
+ input wire [7:0] txa_refclk;
+ input wire [7:0] txb_refclk;
+ input wire [7:0] rxa_refclk;
+ input wire [7:0] rxb_refclk;
+ input wire [7:0] interp_rate;
+ input wire [7:0] decim_rate;
+ input wire [7:0] misc;
+ input wire [31:0] txmux;
+
+ wire [31:0] bundle[43:0];
assign bundle[0] = 32'hFFFFFFFF;
assign bundle[1] = 32'hFFFFFFFF;
assign bundle[2] = {20'd0, atr_tx_delay};
@@ -65,58 +97,57 @@
assign bundle[42] = {24'd0, txb_refclk};
assign bundle[43] = {24'd0, rxb_refclk};
- reg strobe;
- wire [31:0] out[7:0];
- assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
- assign threshhold = out[1];
- assign rssi_wait = out[2];
- assign strobe_wr = strobe;
+ reg strobe;
+ wire [31:0] out[7:0];
+ assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
+ assign threshhold = out[1];
+ assign rssi_wait = out[2];
+ assign strobe_wr = strobe;
- always @(*)
- if (reset | ~enable[1])
- begin
- strobe <= 0;
- dataout <= 0;
- end
- else
- begin
- if (enable[0])
- begin
- //read
- if (addr <= 7'd43)
- dataout <= bundle[addr];
- else if (addr <= 7'd57 && addr >= 7'd50)
- dataout <= out[addr-7'd50];
- else
- dataout <= 32'hFFFFFFFF;
- strobe <= 0;
- end
- else
- begin
- //write
- dataout <= dataout;
- strobe <= 1;
- data_wr <= datain;
- addr_wr <= addr;
- end
- end
+ always @(*)
+ if (reset | ~enable[1])
+ begin
+ strobe <= 0;
+ dataout <= 0;
+ end
+ else
+ begin
+ if (enable[0])
+ begin
+ //read
+ if (addr <= 7'd43)
+ dataout <= bundle[addr];
+ else if (addr <= 7'd57 && addr >= 7'd50)
+ dataout <= out[addr-7'd50];
+ else
+ dataout <= 32'hFFFFFFFF;
+ strobe <= 0;
+ end
+ else
+ begin
+ //write
+ dataout <= dataout;
+ strobe <= 1;
+ data_wr <= datain;
+ addr_wr <= addr;
+ end
+ end
- //user defined registers declarations
- setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[0]));
- setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[1]));
- setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[2]));
- setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[3]));
- setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[4]));
- setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[5]));
- setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[6]));
- setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[7]));
-
+//register declarations
+ setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));
+ setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
+ setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
+ setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
+ setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
+ setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5]));
+ setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
+ setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));
endmodule
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-12-11 22:32:39 UTC (rev 7108)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-12-11 22:34:32 UTC (rev 7109)
@@ -1,144 +1,180 @@
//`include "../../firmware/include/fpga_regs_common.v"
//`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer_inband
- ( //System
- input usbclk, input bus_reset, input reset, // DSP side reset (used
here), do not reset registers
+ ( input usbclk,
+ input bus_reset,
+ input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
- output [15:0] usbdata, input RD, output wire have_pkt_rdy,
- output reg rx_overrun, input wire [3:0] channels,
- input wire [15:0] ch_0, input wire [15:0] ch_1,
- input wire [15:0] ch_2, input wire [15:0] ch_3,
- input wire [15:0] ch_4, input wire [15:0] ch_5,
- input wire [15:0] ch_6, input wire [15:0] ch_7,
- input rxclk, input rxstrobe, input clear_status,
- input [6:0] serial_addr, input [31:0] serial_data,
- input serial_strobe, output wire [15:0] debugbus,
+ output [15:0] usbdata,
+ input RD,
+ output wire have_pkt_rdy,
+ output reg rx_overrun,
+ input wire [3:0] channels,
+ input wire [15:0] ch_0,
+ input wire [15:0] ch_1,
+ input wire [15:0] ch_2,
+ input wire [15:0] ch_3,
+ input wire [15:0] ch_4,
+ input wire [15:0] ch_5,
+ input wire [15:0] ch_6,
+ input wire [15:0] ch_7,
+ input rxclk,
+ input rxstrobe,
+ input clear_status,
+ input [6:0] serial_addr,
+ input [31:0] serial_data,
+ input serial_strobe,
+ output wire [15:0] debugbus,
+
//Connection with tx_inband
- input rx_WR, input [15:0] rx_databus,
- input rx_WR_done, output reg rx_WR_enabled,
+ input rx_WR,
+ input [15:0] rx_databus,
+ input rx_WR_done,
+ output reg rx_WR_enabled,
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- input wire [1:0] tx_underrun);
+ input wire [1:0] tx_underrun
+ );
- parameter NUM_CHAN = 1;
- genvar i ;
+ parameter NUM_CHAN = 1;
+ genvar i ;
- // FX2 Bug Fix
- reg [8:0] read_count;
- always @(negedge usbclk)
- if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
- else
- read_count <= #1 RD ? read_count : 9'b0;
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
- // Time counter
- reg [31:0] adctime;
- always @(posedge rxclk)
- if (reset)
- adctime <= 0;
- else if (rxstrobe)
- adctime <= adctime + 1;
+ // Time counter
+ reg [31:0] adctime;
+ always @(posedge rxclk)
+ if (reset)
+ adctime <= 0;
+ else if (rxstrobe)
+ adctime <= adctime + 1;
- // USB side fifo
- wire [11:0] rdusedw;
- wire [11:0] wrusedw;
- wire [15:0] fifodata;
- wire WR;
- wire have_space;
+ // USB side fifo
+ wire [11:0] rdusedw;
+ wire [11:0] wrusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
- fifo_4kx16_dc rx_usb_fifo
- (.aclr (reset), .data (fifodata),
- .rdclk (~usbclk), .rdreq (RD & ~read_count[8]),
- .wrclk (rxclk), .wrreq (WR), .q (usbdata),
- .rdusedw (rdusedw), .wrusedw (wrusedw));
+ fifo_4kx16_dc rx_usb_fifo (
+ .aclr ( reset ),
+ .data ( fifodata ),
+ .rdclk ( ~usbclk ),
+ .rdreq ( RD & ~read_count[8] ),
+ .wrclk ( rxclk ),
+ .wrreq ( WR ),
+ .q ( usbdata ),
+ .rdempty ( ),
+ .rdusedw ( rdusedw ),
+ .wrfull ( ),
+ .wrusedw ( wrusedw ) );
- assign have_pkt_rdy = (rdusedw >= 12'd256);
- assign have_space = (wrusedw < 12'd760);
+ assign have_pkt_rdy = (rdusedw >= 12'd256);
+ assign have_space = (wrusedw < 12'd760);
- // Rx side fifos
- wire chan_rdreq;
- wire [15:0] chan_fifodata;
- wire [9:0] chan_usedw;
- wire [NUM_CHAN:0] chan_empty;
- wire [3:0] rd_select;
- wire [NUM_CHAN:0] rx_full;
+ // Rx side fifos
+ wire chan_rdreq;
+ wire [15:0] chan_fifodata;
+ wire [9:0] chan_usedw;
+ wire [NUM_CHAN:0] chan_empty;
+ wire [3:0] rd_select;
+ wire [NUM_CHAN:0] rx_full;
- packet_builder #(NUM_CHAN) rx_pkt_builer
- (.rxclk (rxclk), .reset (reset),
- .adctime (adctime), .channels (4'd1),
- .chan_rdreq (chan_rdreq), .chan_fifodata (chan_fifodata),
- .chan_empty (chan_empty), .rd_select (rd_select),
- .chan_usedw (chan_usedw), .WR (WR), .fifodata (fifodata),
- .have_space (have_space), .rssi_0(rssi_0), .rssi_1(rssi_1),
- .rssi_2(rssi_2), .rssi_3(rssi_3), .debugbus(debug),
.underrun(tx_underrun));
+ packet_builder #(NUM_CHAN) rx_pkt_builer (
+ .rxclk ( rxclk ),
+ .reset ( reset ),
+ .adctime ( adctime ),
+ .channels ( 4'd1 ), //need to be tested and changed to channels
+ .chan_rdreq ( chan_rdreq ),
+ .chan_fifodata ( chan_fifodata ),
+ .chan_empty ( chan_empty ),
+ .rd_select ( rd_select ),
+ .chan_usedw ( chan_usedw ),
+ .WR ( WR ),
+ .fifodata ( fifodata ),
+ .have_space ( have_space ),
+ .rssi_0(rssi_0), .rssi_1(rssi_1),
+ .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
+ .underrun(tx_underrun));
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(rx_full[0])
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
+ // Detect overrun
- reg [6:0] test;
-
- always @(posedge rxclk)
- if (reset)
- test <= 0;
- else
- test <= test + 7'd1;
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rx_full[0])
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
+
- // TODO write this genericly
- wire [15:0]ch[NUM_CHAN:0];
- assign ch[0] = ch_0;
-
- wire cmd_empty;
+ // TODO write this genericly
+ wire [15:0]ch[NUM_CHAN:0];
+ assign ch[0] = ch_0;
- always @(posedge rxclk)
- if(reset)
- rx_WR_enabled <= 1;
- else if(cmd_empty)
- rx_WR_enabled <= 1;
- else if(rx_WR_done)
- rx_WR_enabled <= 0;
+ wire cmd_empty;
- wire [15:0] dataout [0:NUM_CHAN];
- wire [9:0] usedw [0:NUM_CHAN];
- wire empty [0:NUM_CHAN];
+ always @(posedge rxclk)
+ if(reset)
+ rx_WR_enabled <= 1;
+ else if(cmd_empty)
+ rx_WR_enabled <= 1;
+ else if(rx_WR_done)
+ rx_WR_enabled <= 0;
+
+ wire [15:0] dataout [0:NUM_CHAN];
+ wire [9:0] usedw [0:NUM_CHAN];
+ wire empty[0:NUM_CHAN];
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
- begin : generate_channel_fifos
-
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ begin : generate_channel_fifos
+
wire rdreq;
+
assign rdreq = (rd_select == i) & chan_rdreq;
- fifo_1kx16 rx_chan_fifo
- (.aclr (reset), .clock (rxclk), .data (ch[i]),
- .rdreq (rdreq), .wrreq (~rx_full[i] & rxstrobe),
- .empty (empty[i]), .full (rx_full[i]), .q ( dataout[i]),
- .usedw ( usedw[i]), .almost_empty(chan_empty[i]));
-
- end
-
- endgenerate
+ fifo_1kx16 rx_chan_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( ch[i] ),
+ .rdreq ( rdreq ),
+ .wrreq ( ~rx_full[i] & rxstrobe),
+ .empty (empty[i]),
+ .full (rx_full[i]),
+ .q ( dataout[i]),
+ .usedw ( usedw[i]),
+ .almost_empty(chan_empty[i])
+ );
+ end
+ endgenerate
- wire [7:0] debug;
-
- fifo_1kx16 rx_cmd_fifo
- (.aclr (reset), .clock (rxclk), .data (rx_databus),
- .rdreq ((rd_select == NUM_CHAN) & chan_rdreq),
- .wrreq (rx_WR & rx_WR_enabled), .empty(cmd_empty),
- .full (rx_full[NUM_CHAN]),
- .q ( dataout[NUM_CHAN]), .usedw (usedw[NUM_CHAN]));
+ wire [7:0] debug;
+
+ fifo_1kx16 rx_cmd_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( rx_databus ),
+ .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
+ .wrreq ( rx_WR & rx_WR_enabled),
+ .empty ( cmd_empty),
+ .full ( rx_full[NUM_CHAN] ),
+ .q ( dataout[NUM_CHAN]),
+ .usedw ( usedw[NUM_CHAN] )
+ );
+
+ assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+ assign chan_fifodata = dataout[rd_select];
+ assign chan_usedw = usedw[rd_select];
+ assign debugbus = {4'd0, rxclk, debug, chan_usedw==0, rx_full[0],
chan_empty[0]};
+
- assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
- assign chan_fifodata = dataout[rd_select];
- assign chan_usedw = usedw[rd_select];
- assign debugbus = {rxstrobe, chan_rdreq, debug,
- rx_full[0], chan_empty[0], empty[0], have_space, RD,
rxclk};
-
endmodule
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-12-11 22:32:39 UTC (rev 7108)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-12-11 22:34:32 UTC (rev 7109)
@@ -13,7 +13,7 @@
output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
input wire rx_WR_enabled,
//register io
- output wire reg_io_enable, output wire [31:0] reg_data_in, output wire
[6:0] reg_addr,
+ output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output
wire [6:0] reg_addr,
input wire [31:0] reg_data_out,
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0]
rssi_2,
@@ -33,8 +33,8 @@
/* These will eventually be external register */
reg [31:0] adc_time ;
- wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
- wire [31:0] rssi [3:0];
+ wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
+ wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
assign rssi[2] = rssi_2;
@@ -55,8 +55,8 @@
/* Connections between data block and the
FX2/TX chains */
- wire [NUM_CHAN:0] chan_underrun ;
- wire [NUM_CHAN:0] chan_txempty ;
+ wire [NUM_CHAN:0] chan_underrun;
+ wire [NUM_CHAN:0] chan_txempty;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
@@ -64,10 +64,10 @@
wire chan_pkt_waiting [NUM_CHAN:0] ;
wire chan_rdreq [NUM_CHAN:0] ;
wire chan_skip [NUM_CHAN:0] ;
- wire [NUM_CHAN:0] chan_have_space ;
+ wire chan_have_space [NUM_CHAN:0] ;
wire chan_txstrobe [NUM_CHAN-1:0] ;
- wire [14:0] debug;
+ wire [14:0] debug [NUM_CHAN:0];
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
@@ -90,7 +90,9 @@
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
- assign debugbus = {debug, txclk};
+ assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
+ chan_pkt_waiting[0], chan_pkt_waiting[1],
+ chan_rdreq[0], chan_rdreq[1], chan_txempty[0],
chan_txempty[1]};
wire [31:0] usbdata_final;
wire WR_final;
@@ -122,7 +124,7 @@
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
- .tx_empty(chan_txempty[i]), .rssi(rssi[i]),
+ .tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
.threshhold(threshhold), .rssi_wait(rssi_wait));
end
endgenerate
@@ -140,7 +142,7 @@
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out),
.reg_addr(reg_addr),
- .reg_io_enable(reg_io_enable), .debug(debug), .stop(stop),
.stop_time(stop_time));
+ .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop),
.stop_time(stop_time));
endmodule // tx_buffer
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16.bsf
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16.bsf
2007-12-11 22:32:39 UTC (rev 7108)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16.bsf
2007-12-11 22:34:32 UTC (rev 7109)
@@ -95,7 +95,7 @@
)
(drawing
(text "16 bits x 1024 words" (rect 58 132 144 144)(font "Arial"
))
- (text "almost_empty < 126" (rect 58 122 144 134)(font "Arial" ))
+ (text "almost_empty < 504" (rect 58 122 144 134)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 144)(line_width 1))
(line (pt 144 144)(pt 16 144)(line_width 1))
Modified: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16.v
2007-12-11 22:32:39 UTC (rev 7108)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16.v
2007-12-11 22:34:32 UTC (rev 7109)
@@ -86,7 +86,7 @@
);
defparam
scfifo_component.add_ram_output_register = "OFF",
- scfifo_component.almost_empty_value = 126,
+ scfifo_component.almost_empty_value = 504,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
@@ -105,7 +105,7 @@
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
@@ -133,7 +133,7 @@
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126"
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16_bb.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16_bb.v
2007-12-11 22:32:39 UTC (rev 7108)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1kx16_bb.v
2007-12-11 22:34:32 UTC (rev 7109)
@@ -57,7 +57,7 @@
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
@@ -85,7 +85,7 @@
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126"
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev2/std_inband.rbf
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/rbf/rev4/std_inband.rbf
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2007-12-11 22:32:39 UTC (rev 7108)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2007-12-11 22:34:32 UTC (rev 7109)
@@ -31,10 +31,10 @@
// ====================================================================
// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel
- `include "../include/common_config_1rxhb_1tx.vh"
+// `include "../include/common_config_1rxhb_1tx.vh"
// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
-//`include "../include/common_config_2rxhb_2tx.vh"
+`include "../include/common_config_2rxhb_2tx.vh"
// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
//`include "../include/common_config_4rx_0tx.vh"
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-12-11 22:32:39 UTC (rev 7108)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-12-11 22:34:32 UTC (rev 7109)
@@ -150,7 +150,7 @@
.reg_data_out(reg_data_out),
.reg_data_in(reg_data_in),
.reg_io_enable(reg_io_enable),
- .debugbus(),
+ .debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.stop(stop), .stop_time(stop_time));
@@ -263,12 +263,11 @@
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
-
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
- .debugbus(tx_debugbus),
+ .debugbus(),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`else
@@ -361,12 +360,12 @@
wire [6:0] addr_db;
wire [31:0] data_db;
wire strobe_db;
- //assign serial_strobe = strobe_db | strobe_wr;
- //assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
- //assign serial_data = (strobe_db)? (data_db) : (data_wr);
- assign serial_strobe = strobe_wr;
- assign serial_data = data_wr;
- assign serial_addr = addr_wr;
+ assign serial_strobe = strobe_db | strobe_wr;
+ assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
+ assign serial_data = (strobe_db)? (data_db) : (data_wr);
+ //assign serial_strobe = strobe_wr;
+ //assign serial_data = data_wr;
+ //assign serial_addr = addr_wr;
//wires for register connection
wire [11:0] atr_tx_delay;
@@ -388,7 +387,8 @@
wire [7:0] txa_refclk;
wire [7:0] txb_refclk;
wire [7:0] rxa_refclk;
- wire [7:0] rxb_refclk;
+ wire [7:0] rxb_refclk;
+
register_io register_control
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
.dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr),
.strobe_wr(strobe_wr),
@@ -404,6 +404,8 @@
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3),
.atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk),
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
+
+ //implementing freeze mode
reg [15:0] timestop;
wire stop;
wire [15:0] stop_time;
@@ -432,7 +434,8 @@
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1),
.atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2),
.atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3),
.atr_rxval_3(atr_rxval_3),
- .txa_refclk(txa_refclk), .txb_refclk(txb_refclk),
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
+ .txa_refclk(txa_refclk), .txb_refclk(txb_refclk),
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
+ .debug_0(tx_debugbus), .debug_1(rx_debugbus));
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
@@ -443,5 +446,9 @@
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc Settings
setting_reg #(`FR_MODE)
sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
-
+ reg forb;
+ always @(posedge usbclk)
+ begin
+ if (strobe_db) forb <= 1;
+ end
endmodule // usrp_inband_usb
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
2007-12-11 22:32:39 UTC (rev 7108)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
2007-12-11 22:34:32 UTC (rev 7109)
@@ -27,7 +27,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13,
2003"
-set_global_assignment -name LAST_QUARTUS_VERSION 7.0
+set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1"
# Pin & Location Assignments
# ==========================
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- [Commit-gnuradio] r7109 - in gnuradio/branches/features/inband-usb/usrp/fpga: inband_lib megacells rbf/rev2 rbf/rev4 toplevel/usrp_inband_usb toplevel/usrp_std,
gnychis <=