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[Commit-gnuradio] r7104 - in gnuradio/branches/developers/zhuochen/inban
From: |
zhuochen |
Subject: |
[Commit-gnuradio] r7104 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib toplevel/usrp_inband_usb |
Date: |
Tue, 11 Dec 2007 09:21:52 -0700 (MST) |
Author: zhuochen
Date: 2007-12-11 09:21:51 -0700 (Tue, 11 Dec 2007)
New Revision: 7104
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_demux.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
Work in progress on fixing two data channels
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-12-11 03:52:02 UTC (rev 7103)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-12-11 16:21:51 UTC (rev 7104)
@@ -21,7 +21,7 @@
input wire [31:0] rssi_wait;
output wire [14:0] debug;
- assign debug = {reader_state, trash, skip, timestamp[4:0], adc_time[4:0]};
+ assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe,
tx_clock};
// Should not be needed if adc clock rate < tx clock rate
// Used only to debug
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_demux.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_demux.v
2007-12-11 03:52:02 UTC (rev 7103)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_demux.v
2007-12-11 16:21:51 UTC (rev 7104)
@@ -1,13 +1,13 @@
module channel_demux
- #(parameter NUM_CHAN = 2, parameter CHAN_WIDTH = 2) ( //usb Side
+ #(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
- output reg [CHAN_WIDTH:0] WR_channel,
+ output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
- output reg [CHAN_WIDTH:0] WR_done_channel );
+ output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
reg [2:0]reader_state;
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-12-11 03:52:02 UTC (rev 7103)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-12-11 16:21:51 UTC (rev 7104)
@@ -55,8 +55,8 @@
/* Connections between data block and the
FX2/TX chains */
- wire [NUM_CHAN:0] chan_underrun ;
- wire [NUM_CHAN:0] chan_txempty ;
+ wire [NUM_CHAN:0] chan_underrun;
+ wire [NUM_CHAN:0] chan_txempty;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
@@ -64,10 +64,10 @@
wire chan_pkt_waiting [NUM_CHAN:0] ;
wire chan_rdreq [NUM_CHAN:0] ;
wire chan_skip [NUM_CHAN:0] ;
- wire [NUM_CHAN:0] chan_have_space ;
+ wire chan_have_space [NUM_CHAN:0] ;
wire chan_txstrobe [NUM_CHAN-1:0] ;
- wire [14:0] debug;
+ wire [14:0] debug [NUM_CHAN:0];
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
@@ -90,7 +90,9 @@
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
- assign debugbus = {debug, txclk};
+ assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
+ chan_pkt_waiting[0], chan_pkt_waiting[1],
chan_pkt_waiting[2],
+ chan_rdreq[0], chan_rdreq[1], chan_rdreq[2]};
wire [31:0] usbdata_final;
wire WR_final;
@@ -122,7 +124,7 @@
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
- .tx_empty(chan_txempty[i]), .rssi(rssi[i]),
+ .tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
.threshhold(threshhold), .rssi_wait(rssi_wait));
end
endgenerate
@@ -140,7 +142,7 @@
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out),
.reg_addr(reg_addr),
- .reg_io_enable(reg_io_enable), .debug(debug), .stop(stop),
.stop_time(stop_time));
+ .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop),
.stop_time(stop_time));
endmodule // tx_buffer
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2007-12-11 03:52:02 UTC (rev 7103)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2007-12-11 16:21:51 UTC (rev 7104)
@@ -31,10 +31,10 @@
// ====================================================================
// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel
- `include "../include/common_config_1rxhb_1tx.vh"
+// `include "../include/common_config_1rxhb_1tx.vh"
// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
-//`include "../include/common_config_2rxhb_2tx.vh"
+`include "../include/common_config_2rxhb_2tx.vh"
// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
//`include "../include/common_config_4rx_0tx.vh"
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-12-11 03:52:02 UTC (rev 7103)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-12-11 16:21:51 UTC (rev 7104)
@@ -150,7 +150,7 @@
.reg_data_out(reg_data_out),
.reg_data_in(reg_data_in),
.reg_io_enable(reg_io_enable),
- .debugbus(),
+ .debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.stop(stop), .stop_time(stop_time));
@@ -267,7 +267,7 @@
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
- .debugbus(tx_debugbus),
+ .debugbus(),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`else
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