[Commit-gnuradio] r7097 - usrp2/trunk/fpga/eth/rtl/verilog

[matt]

Author: matt
Date: 2007-12-10 01:53:18 -0700 (Mon, 10 Dec 2007)
New Revision: 7097

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v
   usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_tx.v
Log:
progress, still not fully functional


Modified: usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v     2007-12-10 05:53:16 UTC 
(rev 7096)
+++ usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v     2007-12-10 08:53:18 UTC 
(rev 7097)
@@ -37,9 +37,9 @@
    // 
******************************************************************************
 
    reg xon_int, xoff_int;
-   reg [15:0] countdown;
+   reg [21:0] countdown;
  
-   always @(posedge rx_clk)
+   always @(posedge rx_clk or posedge rst)
      if(rst)
        begin
          xon_int <= 0;
@@ -52,22 +52,14 @@
          xoff_int <= 0;
          if(countdown == 0)
            if(rx_fifo_space < fc_lwmark)
-             begin
-                xon_int <= 1;
-                countdown <= 250;
-             end
+             xoff_int <= 1;
            else
              ;
          else
            if(rx_fifo_space > fc_hwmark)
-             begin
-                xoff_int <= 1;
-                countdown <= 0;
-             end
-           else
-             countdown <= countdown - 1;
+             xon_int <= 1;
        end // else: !if(rst)
-
+   
    reg xoff_int_d1, xon_int_d1;
 
    always @(posedge rx_clk)
@@ -91,4 +83,16 @@
      else if (xon_int | xon_int_d1)
        xon_gen     <=1;                     
 
+   wire [15:0] pq_reduced = pause_quanta_set - 2;
+   
+   always @(posedge tx_clk or posedge rst)
+     if(rst)
+       countdown <= 0;
+     else if(xoff_gen)
+       countdown <= {pq_reduced,6'd0};
+     else if(xon_gen)
+       countdown <= 0;
+     else if(countdown != 0)
+       countdown <= countdown - 1;
+   
 endmodule // flow_ctrl

Modified: usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_tx.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_tx.v     2007-12-10 05:53:16 UTC 
(rev 7096)
+++ usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_tx.v     2007-12-10 08:53:18 UTC 
(rev 7097)
@@ -19,8 +19,11 @@
 
    reg [15:0]  pause_quanta_counter;
    reg                 pqval_d1, pqval_d2;             
-   
-   always @ (posedge tx_clk)
+
+   always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;
+   always @(posedge tx_clk) pqval_d2 <= pqval_d1;
+
+   always @ (posedge tx_clk or posedge rst)
      if (rst)
        pause_quanta_counter <= 0;
      else if (pqval_d1 & ~pqval_d2)