[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r7093 - in usrp2/trunk/fpga/eth/rtl/verilog: . MAC_rx
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r7093 - in usrp2/trunk/fpga/eth/rtl/verilog: . MAC_rx MAC_tx |
|
Date: |
Sun, 9 Dec 2007 22:46:31 -0700 (MST) |
Author: matt
Date: 2007-12-09 22:46:30 -0700 (Sun, 09 Dec 2007)
New Revision: 7093
Added:
usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v
usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_tx.v
Removed:
usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/flow_ctrl.v
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx.v
usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v
usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx.v
usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v
Log:
massive changes to fix flow control. flow_ctrl_rx.v is not complete yet
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2007-12-10 04:38:23 UTC
(rev 7092)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v 2007-12-10 05:46:30 UTC
(rev 7093)
@@ -61,63 +61,36 @@
`include "header.vh"
-module MAC_rx_FF (
- Reset,
- Clk_MAC,
- Clk_SYS,
-
- // MAC_rx_ctrl interface
- Fifo_data,
- Fifo_data_en,
- Fifo_full,
- Fifo_data_err,
- Fifo_data_drop,
- Fifo_data_end,
-
- // CPU
- Rx_Hwmark,
- Rx_Lwmark,
- RX_APPEND_CRC,
-
- // User interface
- Rx_mac_ra,
- Rx_mac_rd,
- Rx_mac_data,
- Rx_mac_BE,
- Rx_mac_sop,
- Rx_mac_pa,
- Rx_mac_err,
- Rx_mac_eop
-);
-
- input Reset;
- input Clk_MAC;
- input Clk_SYS;
-
- // MAC_rx_ctrl interface
- input [7:0] Fifo_data;
- input Fifo_data_en;
- output Fifo_full;
- input Fifo_data_err;
- input Fifo_data_drop;
- input Fifo_data_end;
-
- // CPU
- input RX_APPEND_CRC;
- input [4:0] Rx_Hwmark;
- input [4:0] Rx_Lwmark;
-
- // User interface
- output Rx_mac_ra;
- input Rx_mac_rd;
- output [31:0] Rx_mac_data;
- output [1:0] Rx_mac_BE;
- output Rx_mac_pa;
- output Rx_mac_sop;
- output Rx_mac_err;
- output Rx_mac_eop;
-
- parameter RX_FF_DEPTH = 9;
+module MAC_rx_FF
+ #(parameter RX_FF_DEPTH = 9)
+ (input Reset,
+ input Clk_MAC,
+ input Clk_SYS,
+
+ // MAC_rx_ctrl interface
+ input [7:0] Fifo_data,
+ input Fifo_data_en,
+ output Fifo_full,
+ input Fifo_data_err,
+ input Fifo_data_drop,
+ input Fifo_data_end,
+ output [15:0] Fifo_space,
+
+ // CPU
+ input RX_APPEND_CRC,
+ input [4:0] Rx_Hwmark,
+ input [4:0] Rx_Lwmark,
+
+ // User interface
+ output Rx_mac_ra,
+ input Rx_mac_rd,
+ output [31:0] Rx_mac_data,
+ output [1:0] Rx_mac_BE,
+ output Rx_mac_pa,
+ output Rx_mac_sop,
+ output Rx_mac_err,
+ output Rx_mac_eop );
+
//-------------------------------------------------------------------------
// Internal signals
//-------------------------------------------------------------------------
@@ -368,7 +341,9 @@
assign Fifo_full = Almost_full;
- //
+ wire [RX_FF_DEPTH-1:0] Fifo_space_int = (Add_rd_ungray - Add_wr);
+ assign Fifo_space =
{{(16-RX_FF_DEPTH){1'b0}},Fifo_space_int};
+
always @( posedge Clk_MAC or posedge Reset )
if ( Reset )
begin
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v 2007-12-10
04:38:23 UTC (rev 7092)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v 2007-12-10
05:46:30 UTC (rev 7093)
@@ -632,7 +632,9 @@
pause_quanta <=0;
else if(Pause_current==Pause_quanta_lo)
pause_quanta <={pause_quanta_h,RxD_dl1};
-
+
+ // The following 2 always blocks are a strange way of holding
+ // pause_quanta_val high for 2 cycles
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_val_tmp <=0;
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx.v 2007-12-10 04:38:23 UTC (rev
7092)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx.v 2007-12-10 05:46:30 UTC (rev
7093)
@@ -64,8 +64,9 @@
input [7:0] MRxD ,
input MRxErr ,
//flow_control signals
-output [15:0] pause_quanta ,
-output pause_quanta_val ,
+output [15:0] pause_quanta,
+output pause_quanta_val,
+output [15:0] rx_fifo_space,
//user interface
output Rx_mac_ra ,
input Rx_mac_rd ,
@@ -111,9 +112,6 @@
//broadcast_filter
wire broadcast_ptr ;
wire broadcast_drop ;
- //flow_control signals
-//wire [15:0] pause_quanta ;
-//wire pause_quanta_val ;
//MAC_rx_ctrl interface
wire [7:0] Fifo_data ;
wire Fifo_data_en ;
@@ -179,6 +177,7 @@
.Fifo_data_err (Fifo_data_err ),
.Fifo_data_drop (Fifo_data_drop ),
.Fifo_data_end (Fifo_data_end ),
+.Fifo_space (rx_fifo_space ),
//CPU (//CPU ),
.Rx_Hwmark (Rx_Hwmark ),
.Rx_Lwmark (Rx_Lwmark ),
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v 2007-12-10 04:38:23 UTC (rev
7092)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v 2007-12-10 05:46:30 UTC (rev
7093)
@@ -128,10 +128,14 @@
wire [7:0] MRxD;
wire MRxErr;
- // Flow-control signals
- wire [15:0] pause_quanta;
- wire pause_quanta_val;
-
+ // Flow-control signals
+ wire [15:0] pause_quanta;
+ wire pause_quanta_val;
+ wire [15:0] rx_fifo_space;
+ wire pause_apply, pause_quanta_sub;
+ wire xon_gen, xoff_gen, xon_gen_complete, xoff_gen_complete;
+ wire [15:0] fc_hwmark, fc_lwmark;
+
//PHY interface
wire [7:0] MTxD;
wire MTxEn;
@@ -156,8 +160,6 @@
wire [2:0] MAC_tx_add_prom_add;
wire MAC_tx_add_prom_wr;
wire tx_pause_en;
- wire xoff_cpu;
- wire xon_cpu;
// Rx host interface
wire MAC_rx_add_chk_en;
@@ -219,7 +221,8 @@
// Flow-control signals
.pause_quanta ( pause_quanta ),
.pause_quanta_val ( pause_quanta_val ),
-
+ .rx_fifo_space ( rx_fifo_space ),
+
// User interface
.Rx_mac_ra ( Rx_mac_ra ),
.Rx_mac_rd ( Rx_mac_rd ),
@@ -281,8 +284,6 @@
// Host interface
.Tx_Hwmark ( Tx_Hwmark ),
.Tx_Lwmark ( Tx_Lwmark ),
- .pause_frame_send_en ( pause_frame_send_en ),
- .pause_quanta_set ( pause_quanta_set ),
.MAC_tx_add_en ( MAC_tx_add_en ),
.FullDuplex ( FullDuplex ),
.MaxRetry ( MaxRetry ),
@@ -290,15 +291,48 @@
.MAC_add_prom_data ( MAC_tx_add_prom_data ),
.MAC_add_prom_add ( MAC_tx_add_prom_add ),
.MAC_add_prom_wr ( MAC_tx_add_prom_wr ),
- .tx_pause_en ( tx_pause_en ),
- .xoff_cpu ( xoff_cpu ),
- .xon_cpu ( xon_cpu ),
- // MAC_rx_flow
- .pause_quanta ( pause_quanta ),
- .pause_quanta_val ( pause_quanta_val )
+ .pause_apply ( pause_apply ),
+ .pause_quanta_sub ( pause_quanta_sub ),
+ .pause_quanta_set ( pause_quanta_set ),
+ .xoff_gen ( xoff_gen ),
+ .xon_gen ( xon_gen ),
+ .xoff_gen_complete ( xoff_gen_complete ),
+ .xon_gen_complete ( xon_gen_complete )
);
+ // Flow control outbound -- when other side sends PAUSE, we wait
+ flow_ctrl_tx flow_ctrl_tx
+ (.rst(Reset),
+ .tx_clk(MAC_tx_clk_div),
+ // Setting
+ .tx_pause_en ( tx_pause_en ),
+ // From RX side
+ .pause_quanta (pause_quanta),
+ .pause_quanta_val(pause_quanta_val), // Other guy sent a PAUSE
+ // To TX side
+ .pause_apply (pause_apply), // To TX, stop sending new frames
+ .pause_quanta_sub (pause_quanta_sub) // From TX, indicates we have used
up 1 quanta
+ );
+
+ flow_ctrl_rx flow_ctrl_rx // When we are running out of RX space, send a
PAUSE
+ (.rst(Reset),
+ // Settings
+ .pause_frame_send_en ( pause_frame_send_en ),
+ .pause_quanta_set ( pause_quanta_set ),
+ .fc_hwmark (fc_hwmark),
+ .fc_lwmark (fc_lwmark),
+ // From RX side
+ .rx_clk(MAC_rx_clk_div),
+ .rx_fifo_space (rx_fifo_space), // Decide if we need to send a PAUSE
+ // To TX side
+ .tx_clk(MAC_tx_clk_div),
+ .xoff_gen (xoff_gen),
+ .xon_gen(xon_gen), // Tell our TX to send PAUSE frames
+ .xoff_gen_complete (xoff_gen_complete),
+ .xon_gen_complete(xon_gen_complete)
+ );
+
RMON U_RMON(
.Clk ( CLK_I ),
.Reset ( Reset ),
@@ -408,8 +442,6 @@
// Tx host interface
.Tx_Hwmark ( Tx_Hwmark ),
.Tx_Lwmark ( Tx_Lwmark ),
- .pause_frame_send_en ( pause_frame_send_en ),
- .pause_quanta_set ( pause_quanta_set ),
.MAC_tx_add_en ( MAC_tx_add_en ),
.FullDuplex ( FullDuplex ),
.MaxRetry ( MaxRetry ),
@@ -417,9 +449,6 @@
.MAC_tx_add_prom_data ( MAC_tx_add_prom_data ),
.MAC_tx_add_prom_add ( MAC_tx_add_prom_add ),
.MAC_tx_add_prom_wr ( MAC_tx_add_prom_wr ),
- .tx_pause_en ( tx_pause_en ),
- .xoff_cpu ( xoff_cpu ),
- .xon_cpu ( xon_cpu ),
// Rx host interface
.MAC_rx_add_chk_en ( MAC_rx_add_chk_en ),
@@ -437,6 +466,13 @@
.RX_MAX_LENGTH ( RX_MAX_LENGTH ),
.RX_MIN_LENGTH ( RX_MIN_LENGTH ),
+ // Flow Control settings
+ .pause_frame_send_en ( pause_frame_send_en ),
+ .pause_quanta_set ( pause_quanta_set ),
+ .tx_pause_en ( tx_pause_en ),
+ .fc_hwmark ( fc_hwmark ),
+ .fc_lwmark ( fc_lwmark ),
+
// RMON host interface
.CPU_rd_addr ( CPU_rd_addr ),
.CPU_rd_apply ( CPU_rd_apply ),
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v 2007-12-10
04:38:23 UTC (rev 7092)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v 2007-12-10
05:46:30 UTC (rev 7093)
@@ -101,7 +101,6 @@
Tx_apply_rmon ,
Tx_pkt_err_type_rmon,
//CPU
-pause_frame_send_en ,
pause_quanta_set ,
MAC_tx_add_en ,
FullDuplex ,
@@ -153,7 +152,6 @@
output Tx_apply_rmon ;
output [2:0] Tx_pkt_err_type_rmon;
//CPU
-input pause_frame_send_en ;
input [15:0] pause_quanta_set ;
input MAC_tx_add_en ;
input FullDuplex ;
@@ -210,7 +208,6 @@
reg PktDrpEvenPtr ;
reg [7:0] pause_counter ;
reg pause_quanta_sub ;
-reg pause_frame_send_en_dl1 ;
reg [15:0] pause_quanta_set_dl1 ;
reg xoff_gen_complete ;
reg xon_gen_complete ;
@@ -220,12 +217,10 @@
always @(posedge Clk or posedge Reset)
if (Reset)
begin
- pause_frame_send_en_dl1 <=0;
pause_quanta_set_dl1 <=0;
end
else
begin
- pause_frame_send_en_dl1 <=pause_frame_send_en ;
pause_quanta_set_dl1 <=pause_quanta_set ;
end
//******************************************************************************
@@ -235,14 +230,6 @@
always @(posedge Clk or posedge Reset)
if (Reset)
- pause_counter <=0;
- else if (Current_state!=StatePause)
- pause_counter <=0;
- else
- pause_counter <=pause_counter+1;
-
-always @(posedge Clk or posedge Reset)
- if (Reset)
IPLengthCounter <=0;
else if (Current_state==StateDefer)
IPLengthCounter <=0;
@@ -282,7 +269,7 @@
Next_state=StateDefer;
else if (pause_apply)
Next_state=StatePause;
- else if
((FullDuplex&&Fifo_ra)||(!FullDuplex&&!CRS&&Fifo_ra)||(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)))
+ else if (((FullDuplex||~CRS)&&Fifo_ra)||(xoff_gen||xon_gen))
Next_state=StatePreamble;
else
Next_state=Current_state;
@@ -301,7 +288,7 @@
StateSFD:
if (!FullDuplex&&Collision)
Next_state=StateJam;
- else if (pause_frame_send_en_dl1&&(xoff_gen||xon_gen))
+ else if (xoff_gen||xon_gen)
Next_state=StateSendPauseFrame;
else
Next_state=StateData;
@@ -438,7 +425,7 @@
//data have one cycle delay after fifo read signals
always @ (*)
if (Current_state==StateData ||
-
Current_state==StateSFD&&!(pause_frame_send_en_dl1&&(xoff_gen||xon_gen)) ||
+ Current_state==StateSFD&&!(xoff_gen||xon_gen) ||
Current_state==StateJamDrop&&PktDrpEvenPtr||
Current_state==StateFFEmptyDrop&&PktDrpEvenPtr )
Fifo_rd =1;
@@ -604,11 +591,12 @@
else
MAC_tx_addr_rd <=0;
-always @ (Tx_pkt_length_rmon or Fifo_rd)
- if ((Tx_pkt_length_rmon==3)&&Fifo_rd)
- MAC_tx_addr_init=1;
- else
- MAC_tx_addr_init=0;
+ always @*
+ //if ((Tx_pkt_length_rmon==3)&&Fifo_rd)
+ if (Current_state==StatePreamble)
+ MAC_tx_addr_init=1;
+ else
+ MAC_tx_addr_init=0;
//**************************************************************************************************************
// CFH: this implementation delays the time it sends an entire Ethernet frame
with 512 bits for every pause
@@ -618,6 +606,14 @@
//**************************************************************************************************************
//flow control
+always @(posedge Clk or posedge Reset)
+ if (Reset)
+ pause_counter <=0;
+ else if (Current_state!=StatePause)
+ pause_counter <=0;
+ else
+ pause_counter <=pause_counter+1;
+
always @ (posedge Clk or posedge Reset)
if (Reset)
pause_quanta_sub <=0;
@@ -626,11 +622,12 @@
else
pause_quanta_sub <=0;
-
+// FIXME The below probably won't work if the pause request comes when we are
in the wrong state
+ wire clear_xonxoff = (Current_state==StateSendPauseFrame) &
(IPLengthCounter==17);
always @ (posedge Clk or posedge Reset)
if (Reset)
xoff_gen_complete <=0;
- else if(Current_state==StateDefer&&xoff_gen)
+ else if(clear_xonxoff & xoff_gen)
xoff_gen_complete <=1;
else
xoff_gen_complete <=0;
@@ -639,7 +636,7 @@
always @ (posedge Clk or posedge Reset)
if (Reset)
xon_gen_complete <=0;
- else if(Current_state==StateDefer&&xon_gen)
+ else if(clear_xonxoff & xon_gen)
xon_gen_complete <=1;
else
xon_gen_complete <=0;
Deleted: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/flow_ctrl.v
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx.v 2007-12-10 04:38:23 UTC (rev
7092)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx.v 2007-12-10 05:46:30 UTC (rev
7093)
@@ -78,8 +78,6 @@
//host interface
input [4:0] Tx_Hwmark ,
input [4:0] Tx_Lwmark ,
-input pause_frame_send_en ,
-input [15:0] pause_quanta_set ,
input MAC_tx_add_en ,
input FullDuplex ,
input [3:0] MaxRetry ,
@@ -87,17 +85,20 @@
input [7:0] MAC_add_prom_data ,
input [2:0] MAC_add_prom_add ,
input MAC_add_prom_wr ,
-input tx_pause_en ,
-input xoff_cpu ,
-input xon_cpu ,
- //MAC_rx_flow ,
-input [15:0] pause_quanta ,
-input pause_quanta_val
+ // Flow control stuff
+input pause_apply ,
+output pause_quanta_sub,
+input [15:0] pause_quanta_set ,
+input xoff_gen,
+input xon_gen,
+output xoff_gen_complete,
+output xon_gen_complete
);
-//******************************************************************************
-//internal signals
-//******************************************************************************
- //CRC_gen Interface
+
+ //
******************************************************************************
+ // internal signals
+ //
******************************************************************************
+ //CRC_gen Interface
wire CRC_init ;
wire[7:0] Frame_data ;
wire Data_en ;
@@ -109,12 +110,6 @@
wire[3:0] RetryCnt ;
wire Random_time_meet ;//levle hight indicate random time passed
away
//flow control
-wire pause_apply ;
-wire pause_quanta_sub ;
-wire xoff_gen ;
-wire xoff_gen_complete ;
-wire xon_gen ;
-wire xon_gen_complete ;
//MAC_rx_FF
wire[7:0] Fifo_data ;
wire Fifo_rd ;
@@ -178,7 +173,6 @@
.Tx_apply_rmon (Tx_apply_rmon ),
.Tx_pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
//CPU (//CPU ),
-.pause_frame_send_en (pause_frame_send_en ),
.pause_quanta_set (pause_quanta_set ),
.MAC_tx_add_en (MAC_tx_add_en ),
.FullDuplex (FullDuplex ),
@@ -197,32 +191,13 @@
.CRC_end (CRC_end )
);
-flow_ctrl U_flow_ctrl(
-.Reset (Reset ),
-.Clk (Clk ),
- //host processor (//host processor ),
-.tx_pause_en (tx_pause_en ),
-.xoff_cpu (xoff_cpu ),
-.xon_cpu (xon_cpu ),
- //MAC_rx_flow (//MAC_rx_flow ),
-.pause_quanta (pause_quanta ),
-.pause_quanta_val (pause_quanta_val ),
- //MAC_tx_ctrl (//MAC_tx_ctrl ),
-.pause_apply (pause_apply ),
-.pause_quanta_sub (pause_quanta_sub ),
-.xoff_gen (xoff_gen ),
-.xoff_gen_complete (xoff_gen_complete ),
-.xon_gen (xon_gen ),
-.xon_gen_complete (xon_gen_complete )
-);
-
MAC_tx_addr_add U_MAC_tx_addr_add
(.Reset (Reset ),
.Clk (Clk ),
.MAC_tx_addr_rd (MAC_tx_addr_rd ),
.MAC_tx_addr_init (MAC_tx_addr_init ),
.MAC_tx_addr_data (MAC_tx_addr_data ),
- //CPU (//CPU ),
+ //CPU
.MAC_add_prom_data (MAC_add_prom_data ),
.MAC_add_prom_add (MAC_add_prom_add ),
.MAC_add_prom_wr (MAC_add_prom_wr )
Modified: usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v 2007-12-10 04:38:23 UTC (rev
7092)
+++ usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v 2007-12-10 05:46:30 UTC (rev
7093)
@@ -13,8 +13,6 @@
// Tx host interface
output [4:0] Tx_Hwmark,
output [4:0] Tx_Lwmark,
- output pause_frame_send_en,
- output [15:0] pause_quanta_set,
output MAC_tx_add_en,
output FullDuplex,
output [3:0] MaxRetry,
@@ -22,9 +20,6 @@
output [7:0] MAC_tx_add_prom_data,
output [2:0] MAC_tx_add_prom_add,
output MAC_tx_add_prom_wr,
- output tx_pause_en,
- output xoff_cpu,
- output xon_cpu,
// Rx host interface
output MAC_rx_add_chk_en,
@@ -42,6 +37,13 @@
output [15:0] RX_MAX_LENGTH, // Default 1518
output [6:0] RX_MIN_LENGTH, // Default 64
+ // Flow control settings
+ output pause_frame_send_en,
+ output [15:0] pause_quanta_set,
+ output tx_pause_en,
+ output [15:0] fc_hwmark,
+ output [15:0] fc_lwmark,
+
// RMON host interface
output [5:0] CPU_rd_addr,
output CPU_rd_apply,
@@ -70,42 +72,6 @@
input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with
read data
);
- wire [4:0] Tx_Hwmark_int;
- wire [4:0] Tx_Lwmark_int;
- wire [0:0] pause_frame_send_en_int;
- wire [15:0] pause_quanta_set_int;
- wire [5:0] IFGset_int;
- wire [0:0] FullDuplex_int;
- wire [3:0] MaxRetry_int;
- wire [0:0] MAC_tx_add_en_int;
- wire [7:0] MAC_tx_add_prom_data_int;
- wire [2:0] MAC_tx_add_prom_add_int;
- wire [0:0] MAC_tx_add_prom_wr_int;
- wire [0:0] tx_pause_en_int;
- wire [0:0] xoff_cpu_int;
- wire [0:0] xon_cpu_int;
- wire [0:0] MAC_rx_add_chk_en_int;
- wire [7:0] MAC_rx_add_prom_data_int;
- wire [2:0] MAC_rx_add_prom_add_int;
- wire [0:0] MAC_rx_add_prom_wr_int;
- wire [0:0] broadcast_filter_en_int;
- wire [15:0] broadcast_bucket_depth_int;
- wire [15:0] broadcast_bucket_interval_int;
- wire [0:0] RX_APPEND_CRC_int;
- wire [4:0] Rx_Hwmark_int;
- wire [4:0] Rx_Lwmark_int;
- wire [0:0] CRC_chk_en_int;
- wire [5:0] RX_IFG_SET_int;
- wire [15:0] RX_MAX_LENGTH_int;
- wire [6:0] RX_MIN_LENGTH_int;
- wire [5:0] CPU_rd_addr_int;
- wire [0:0] CPU_rd_apply_int;
-//wire [0:0] CPU_rd_grant_int;
-//wire [15:0] CPU_rd_dout_l_int;
-//wire [15:0] CPU_rd_dout_h_int;
- wire [0:0] Line_loop_en_int;
- wire [2:0] Speed_int;
-
// New registers for controlling the MII interface
wire [8:0] MIIMODER;
reg [2:0] MIICOMMAND;
@@ -114,42 +80,6 @@
reg [15:0] MIIRX_DATA;
wire [2:0] MIISTATUS;
- assign Tx_Hwmark = Tx_Hwmark_int;
- assign Tx_Lwmark = Tx_Lwmark_int;
- assign pause_frame_send_en = pause_frame_send_en_int;
- assign pause_quanta_set = pause_quanta_set_int;
- assign IFGset = IFGset_int;
- assign FullDuplex = FullDuplex_int;
- assign MaxRetry = MaxRetry_int;
- assign MAC_tx_add_en = MAC_tx_add_en_int;
- assign MAC_tx_add_prom_data = MAC_tx_add_prom_data_int;
- assign MAC_tx_add_prom_add = MAC_tx_add_prom_add_int;
- assign MAC_tx_add_prom_wr = MAC_tx_add_prom_wr_int;
- assign tx_pause_en = tx_pause_en_int;
- assign xoff_cpu = xoff_cpu_int;
- assign xon_cpu = xon_cpu_int;
- assign MAC_rx_add_chk_en = MAC_rx_add_chk_en_int;
- assign MAC_rx_add_prom_data = MAC_rx_add_prom_data_int;
- assign MAC_rx_add_prom_add = MAC_rx_add_prom_add_int;
- assign MAC_rx_add_prom_wr = MAC_rx_add_prom_wr_int;
- assign broadcast_filter_en = broadcast_filter_en_int;
- assign broadcast_bucket_depth = broadcast_bucket_depth_int;
- assign broadcast_bucket_interval = broadcast_bucket_interval_int;
- assign RX_APPEND_CRC = RX_APPEND_CRC_int;
- assign Rx_Hwmark = Rx_Hwmark_int;
- assign Rx_Lwmark = Rx_Lwmark_int;
- assign CRC_chk_en = CRC_chk_en_int;
- assign RX_IFG_SET = RX_IFG_SET_int;
- assign RX_MAX_LENGTH = RX_MAX_LENGTH_int;
- assign RX_MIN_LENGTH = RX_MIN_LENGTH_int;
- assign CPU_rd_addr = CPU_rd_addr_int;
- assign CPU_rd_apply = CPU_rd_apply_int;
-//assign CPU_rd_grant = CPU_rd_grant_int;
-//assign CPU_rd_dout_l = CPU_rd_dout_l_int;
-//assign CPU_rd_dout_h = CPU_rd_dout_h_int;
- assign Line_loop_en = Line_loop_en_int;
- assign Speed = Speed_int;
-
// New registers for controlling the MII interface
// MIIMODER
@@ -169,41 +99,41 @@
wire Wr;
- RegCPUData #( 5 ) U_0_000( Tx_Hwmark_int , 7'd000, 5'h09,
RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );
- RegCPUData #( 5 ) U_0_001( Tx_Lwmark_int , 7'd001, 5'h08,
RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );
- RegCPUData #( 1 ) U_0_002( pause_frame_send_en_int , 7'd002, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 16 ) U_0_003( pause_quanta_set_int , 7'd003, 16'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
- RegCPUData #( 6 ) U_0_004( IFGset_int , 7'd004, 6'h0c,
RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] );
- RegCPUData #( 1 ) U_0_005( FullDuplex_int , 7'd005, 1'h1,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 4 ) U_0_006( MaxRetry_int , 7'd006, 4'h2,
RST_I, CLK_I, Wr, ADR_I, DAT_I[3:0] );
- RegCPUData #( 1 ) U_0_007( MAC_tx_add_en_int , 7'd007, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 8 ) U_0_008( MAC_tx_add_prom_data_int , 7'd008, 8'h00,
RST_I, CLK_I, Wr, ADR_I, DAT_I[7:0] );
- RegCPUData #( 3 ) U_0_009( MAC_tx_add_prom_add_int , 7'd009, 3'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] );
- RegCPUData #( 1 ) U_0_010( MAC_tx_add_prom_wr_int , 7'd010, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 1 ) U_0_011( tx_pause_en_int , 7'd011, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 1 ) U_0_012( xoff_cpu_int , 7'd012, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 1 ) U_0_013( xon_cpu_int , 7'd013, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 1 ) U_0_014( MAC_rx_add_chk_en_int , 7'd014, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 8 ) U_0_015( MAC_rx_add_prom_data_int , 7'd015, 8'h00,
RST_I, CLK_I, Wr, ADR_I, DAT_I[7:0] );
- RegCPUData #( 3 ) U_0_016( MAC_rx_add_prom_add_int , 7'd016, 3'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] );
- RegCPUData #( 1 ) U_0_017( MAC_rx_add_prom_wr_int , 7'd017, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 1 ) U_0_018( broadcast_filter_en_int , 7'd018, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 16 ) U_0_019( broadcast_bucket_depth_int , 7'd019, 16'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
- RegCPUData #( 16 ) U_0_020( broadcast_bucket_interval_int, 7'd020, 16'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
- RegCPUData #( 1 ) U_0_021( RX_APPEND_CRC_int , 7'd021, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 5 ) U_0_022( Rx_Hwmark_int , 7'd022, 5'h1a,
RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );
- RegCPUData #( 5 ) U_0_023( Rx_Lwmark_int , 7'd023, 5'h10,
RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );
- RegCPUData #( 1 ) U_0_024( CRC_chk_en_int , 7'd024, 1'h1,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 6 ) U_0_025( RX_IFG_SET_int , 7'd025, 6'h0c,
RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] );
- RegCPUData #( 16 ) U_0_026( RX_MAX_LENGTH_int , 7'd026, 16'h2710,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
- RegCPUData #( 7 ) U_0_027( RX_MIN_LENGTH_int , 7'd027, 7'h40,
RST_I, CLK_I, Wr, ADR_I, DAT_I[6:0] );
- RegCPUData #( 6 ) U_0_028( CPU_rd_addr_int , 7'd028, 6'h00,
RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] );
- RegCPUData #( 1 ) U_0_029( CPU_rd_apply_int , 7'd029, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
-//RegCPUData #( 1 ) U_0_030( CPU_rd_grant_int , 7'd030, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
-//RegCPUData #( 16 ) U_0_031( CPU_rd_dout_l_int , 7'd031, 16'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
-//RegCPUData #( 16 ) U_0_032( CPU_rd_dout_h_int , 7'd032, 16'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
- RegCPUData #( 1 ) U_0_033( Line_loop_en_int , 7'd033, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
- RegCPUData #( 3 ) U_0_034( Speed_int , 7'd034, 3'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] );
+ RegCPUData #( 5 ) U_0_000( Tx_Hwmark , 7'd000, 5'h09,
RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );
+ RegCPUData #( 5 ) U_0_001( Tx_Lwmark , 7'd001, 5'h08,
RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );
+ RegCPUData #( 1 ) U_0_002( pause_frame_send_en , 7'd002, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 16 ) U_0_003( pause_quanta_set , 7'd003, 16'h01af,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
+ RegCPUData #( 6 ) U_0_004( IFGset , 7'd004, 6'h0c,
RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] );
+ RegCPUData #( 1 ) U_0_005( FullDuplex , 7'd005, 1'h1,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 4 ) U_0_006( MaxRetry , 7'd006, 4'h2,
RST_I, CLK_I, Wr, ADR_I, DAT_I[3:0] );
+ RegCPUData #( 1 ) U_0_007( MAC_tx_add_en , 7'd007, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 8 ) U_0_008( MAC_tx_add_prom_data , 7'd008, 8'h00,
RST_I, CLK_I, Wr, ADR_I, DAT_I[7:0] );
+ RegCPUData #( 3 ) U_0_009( MAC_tx_add_prom_add , 7'd009, 3'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] );
+ RegCPUData #( 1 ) U_0_010( MAC_tx_add_prom_wr , 7'd010, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 1 ) U_0_011( tx_pause_en , 7'd011, 1'h1,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 16 ) U_0_012( fc_hwmark , 7'd012, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
+ RegCPUData #( 16 ) U_0_013( fc_lwmark , 7'd013, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
+ RegCPUData #( 1 ) U_0_014( MAC_rx_add_chk_en , 7'd014, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 8 ) U_0_015( MAC_rx_add_prom_data , 7'd015, 8'h00,
RST_I, CLK_I, Wr, ADR_I, DAT_I[7:0] );
+ RegCPUData #( 3 ) U_0_016( MAC_rx_add_prom_add , 7'd016, 3'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] );
+ RegCPUData #( 1 ) U_0_017( MAC_rx_add_prom_wr , 7'd017, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 1 ) U_0_018( broadcast_filter_en , 7'd018, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 16 ) U_0_019( broadcast_bucket_depth , 7'd019, 16'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
+ RegCPUData #( 16 ) U_0_020( broadcast_bucket_interval , 7'd020, 16'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
+ RegCPUData #( 1 ) U_0_021( RX_APPEND_CRC , 7'd021, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 5 ) U_0_022( Rx_Hwmark , 7'd022, 5'h1a,
RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );
+ RegCPUData #( 5 ) U_0_023( Rx_Lwmark , 7'd023, 5'h10,
RST_I, CLK_I, Wr, ADR_I, DAT_I[4:0] );
+ RegCPUData #( 1 ) U_0_024( CRC_chk_en , 7'd024, 1'h1,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 6 ) U_0_025( RX_IFG_SET , 7'd025, 6'h0c,
RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] );
+ RegCPUData #( 16 ) U_0_026( RX_MAX_LENGTH , 7'd026, 16'h2710,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
+ RegCPUData #( 7 ) U_0_027( RX_MIN_LENGTH , 7'd027, 7'h40,
RST_I, CLK_I, Wr, ADR_I, DAT_I[6:0] );
+ RegCPUData #( 6 ) U_0_028( CPU_rd_addr , 7'd028, 6'h00,
RST_I, CLK_I, Wr, ADR_I, DAT_I[5:0] );
+ RegCPUData #( 1 ) U_0_029( CPU_rd_apply , 7'd029, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+//RegCPUData #( 1 ) U_0_030( CPU_rd_grant , 7'd030, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+//RegCPUData #( 16 ) U_0_031( CPU_rd_dout_l , 7'd031, 16'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
+//RegCPUData #( 16 ) U_0_032( CPU_rd_dout_h , 7'd032, 16'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
+ RegCPUData #( 1 ) U_0_033( Line_loop_en , 7'd033, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[0:0] );
+ RegCPUData #( 3 ) U_0_034( Speed , 7'd034, 3'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[2:0] );
// New registers for controlling the MDIO interface
RegCPUData #( 9 ) U_0_035( MIIMODER , 7'd035, 9'h064,
RST_I, CLK_I, Wr, ADR_I, DAT_I[8:0] );
@@ -270,8 +200,8 @@
7'd09: DAT_O <= MAC_tx_add_prom_add;
7'd10: DAT_O <= MAC_tx_add_prom_wr;
7'd11: DAT_O <= tx_pause_en;
- 7'd12: DAT_O <= xoff_cpu;
- 7'd13: DAT_O <= xon_cpu;
+ 7'd12: DAT_O <= fc_hwmark;
+ 7'd13: DAT_O <= fc_lwmark;
7'd14: DAT_O <= MAC_rx_add_chk_en;
7'd15: DAT_O <= MAC_rx_add_prom_data;
7'd16: DAT_O <= MAC_rx_add_prom_add;
Added: usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v
(rev 0)
+++ usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_rx.v 2007-12-10 05:46:30 UTC
(rev 7093)
@@ -0,0 +1,94 @@
+
+// RX side of flow control -- when we are running out of RX space, send a PAUSE
+
+module flow_ctrl_rx
+ (input rst,
+ //host processor
+ input pause_frame_send_en,
+ input [15:0] pause_quanta_set,
+ input [15:0] fc_hwmark,
+ input [15:0] fc_lwmark,
+ // From MAC_rx_ctrl
+ input rx_clk,
+ input [15:0] rx_fifo_space,
+ // MAC_tx_ctrl
+ input tx_clk,
+ output xoff_gen,
+ output xon_gen,
+ input xoff_gen_complete,
+ input xon_gen_complete
+ );
+
+ //
******************************************************************************
+ // internal signals
+ //
******************************************************************************
+ reg [15:0] pause_quanta_dl1 ;
+ reg pause_quanta_val_dl1 ;
+ reg pause_quanta_val_dl2 ;
+ reg pause_apply ;
+ reg xoff_gen ;
+ reg xon_gen ;
+ reg [15:0] pause_quanta_counter ;
+ reg tx_pause_en_dl1 ;
+ reg tx_pause_en_dl2 ;
+
+ //
******************************************************************************
+ // Force our TX to send a PAUSE frame because our RX is nearly full
+ //
******************************************************************************
+
+ reg xon_int, xoff_int;
+ reg [15:0] countdown;
+
+ always @(posedge rx_clk)
+ if(rst)
+ begin
+ xon_int <= 0;
+ xoff_int <= 0;
+ countdown <= 0;
+ end
+ else
+ begin
+ xon_int <= 0;
+ xoff_int <= 0;
+ if(countdown == 0)
+ if(rx_fifo_space < fc_lwmark)
+ begin
+ xon_int <= 1;
+ countdown <= 250;
+ end
+ else
+ ;
+ else
+ if(rx_fifo_space > fc_hwmark)
+ begin
+ xoff_int <= 1;
+ countdown <= 0;
+ end
+ else
+ countdown <= countdown - 1;
+ end // else: !if(rst)
+
+ reg xoff_int_d1, xon_int_d1;
+
+ always @(posedge rx_clk)
+ xon_int_d1 <= xon_int;
+ always @(posedge rx_clk)
+ xoff_int_d1 <= xoff_int;
+
+ always @ (posedge tx_clk or posedge rst)
+ if (rst)
+ xoff_gen <=0;
+ else if (xoff_gen_complete)
+ xoff_gen <=0;
+ else if (xoff_int | xoff_int_d1)
+ xoff_gen <=1;
+
+ always @ (posedge tx_clk or posedge rst)
+ if (rst)
+ xon_gen <=0;
+ else if (xon_gen_complete)
+ xon_gen <=0;
+ else if (xon_int | xon_int_d1)
+ xon_gen <=1;
+
+endmodule // flow_ctrl
Added: usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_tx.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_tx.v
(rev 0)
+++ usrp2/trunk/fpga/eth/rtl/verilog/flow_ctrl_tx.v 2007-12-10 05:46:30 UTC
(rev 7093)
@@ -0,0 +1,33 @@
+
+// TX side of flow control -- when other side sends PAUSE, we wait
+
+module flow_ctrl_tx
+ (input rst,
+ input tx_clk,
+ //host processor
+ input tx_pause_en,
+ // From MAC_rx_ctrl
+ input [15:0] pause_quanta,
+ input pause_quanta_val,
+ // MAC_tx_ctrl
+ output pause_apply,
+ input pause_quanta_sub);
+
+ //
******************************************************************************
+ // Inhibit our TX from transmitting because they sent us a PAUSE frame
+ //
******************************************************************************
+
+ reg [15:0] pause_quanta_counter;
+ reg pqval_d1, pqval_d2;
+
+ always @ (posedge tx_clk)
+ if (rst)
+ pause_quanta_counter <= 0;
+ else if (pqval_d1 & ~pqval_d2)
+ pause_quanta_counter <= pause_quanta;
+ else if((pause_quanta_counter!=0) & pause_quanta_sub)
+ pause_quanta_counter <= pause_quanta_counter - 1;
+
+ assign pause_apply = tx_pause_en & (pause_quanta_counter != 0);
+
+endmodule // flow_ctrl
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r7093 - in usrp2/trunk/fpga/eth/rtl/verilog: . MAC_rx MAC_tx,
matt <=