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[Commit-gnuradio] r7078 - in gnuradio/branches/developers/zhuochen/inban
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From: |
zhuochen |
|
Subject: |
[Commit-gnuradio] r7078 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib megacells |
|
Date: |
Thu, 6 Dec 2007 15:26:28 -0700 (MST) |
Author: zhuochen
Date: 2007-12-06 15:26:28 -0700 (Thu, 06 Dec 2007)
New Revision: 7078
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_demux.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16.bsf
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16_bb.v
Log:
Work in progress on fixing broken command packets
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_demux.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_demux.v
2007-12-06 08:04:21 UTC (rev 7077)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_demux.v
2007-12-06 22:26:28 UTC (rev 7078)
@@ -1,24 +1,24 @@
module channel_demux
#(parameter NUM_CHAN = 2, parameter CHAN_WIDTH = 2) ( //usb Side
- input [31:0]usbdata_final,
- input WR_final,
-
- // TX Side
- input reset,
- input txclk,
- output reg [CHAN_WIDTH:0] WR_channel,
- output reg [31:0] ram_data,
- output reg [CHAN_WIDTH:0] WR_done_channel );
-/* Parse header and forward to ram */
- reg [2:0]reader_state;
- reg [4:0]channel ;
- reg [6:0]read_length ;
+ input [31:0]usbdata_final,
+ input WR_final,
+ // TX Side
+ input reset,
+ input txclk,
+ output reg [CHAN_WIDTH:0] WR_channel,
+ output reg [31:0] ram_data,
+ output reg [CHAN_WIDTH:0] WR_done_channel );
+ /* Parse header and forward to ram */
+ reg [2:0]reader_state;
+ reg [4:0]channel ;
+ reg [6:0]read_length ;
+
// States
- parameter IDLE = 3'd0;
- parameter HEADER = 3'd1;
- parameter WAIT = 3'd2;
- parameter FORWARD = 3'd3;
+ parameter IDLE = 3'd0;
+ parameter HEADER = 3'd1;
+ parameter WAIT = 3'd2;
+ parameter FORWARD = 3'd3;
`define CHANNEL 20:16
`define PKT_SIZE 127
@@ -27,7 +27,7 @@
NUM_CHAN :
(usbdata_final[`CHANNEL]);
always @(posedge txclk)
- begin
+ begin
if (reset)
begin
reader_state <= IDLE;
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
2007-12-06 08:04:21 UTC (rev 7077)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
2007-12-06 22:26:28 UTC (rev 7078)
@@ -1,148 +1,152 @@
-module packet_builder #(parameter NUM_CHAN = 1)
-( //System
- input rxclk, input reset, input [31:0]adctime,
- //ADC side
- input [15:0]chan_fifodata, input [9:0]chan_usedw,
- output reg[3:0]rd_select, output reg chan_rdreq,
- //FX2 side
- output reg WR, output reg [15:0]fifodata, input have_space,
- //misc
- input wire [5:0] rssi, output wire [7:0] debugbus,
- input chan_underrun, input rx_WR_done, output reg rx_WR_enabled);
+module packet_builder #(parameter NUM_CHAN = 1)(
+ // System
+ input rxclk,
+ input reset,
+ input [31:0] adctime,
+ input [3:0] channels,
+ // ADC side
+ input [15:0]chan_fifodata,
+ input [NUM_CHAN:0]chan_empty,
+ input [9:0]chan_usedw,
+ output reg [3:0]rd_select,
+ output reg chan_rdreq,
+ // FX2 side
+ output reg WR,
+ output reg [15:0]fifodata,
+ input have_space,
+ input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
+ input wire [31:0]rssi_3, output wire [7:0] debugbus,
+ input [NUM_CHAN:0] underrun);
+
+
+ // States
+ `define IDLE 3'd0
+ `define HEADER1 3'd1
+ `define HEADER2 3'd2
+ `define TIMESTAMP 3'd3
+ `define FORWARD 3'd4
+
+ `define MAXPAYLOAD 504
+
+ `define PAYLOAD_LEN 8:0
+ `define TAG 12:9
+ `define MBZ 15:13
+
+ `define CHAN 4:0
+ `define RSSI 10:5
+ `define BURST 12:11
+ `define DROPPED 13
+ `define UNDERRUN 14
+ `define OVERRUN 15
+
+ reg [NUM_CHAN:0] overrun;
+ reg [2:0] state;
+ reg [8:0] read_length;
+ reg [8:0] payload_len;
+ reg tstamp_complete;
+ reg [3:0] check_next;
+
+ wire [8:0] chan_used;
+ wire [31:0] true_rssi;
+ wire [4:0] true_channel;
+ wire ready_to_send;
-
- //states
-
- `define IDLE 3'd0
- `define HEADER1 3'd1
- `define HEADER2 3'd2
- `define TIMESTAMP1 3'd3
- `define TIMESTAMP2 3'd4
- `define FORWARD 3'd5
-
- //variables
- `define STDPAYLOAD 9'd504
-
- //packet fields
- `define PAYLOAD_LEN 8:0
- `define TAG 12:9
- `define MBZ 15:13
- `define CHAN 4:0
- `define RSSI 10:5
- `define BURST 12:11
- `define DROPPED 13
- `define UNDERRUN 14
- `define OVERRUN 15
-
- //registers
- reg [2:0] state;
- reg [8:0] payload_len;
- reg [8:0] payload_read;
- reg [NUM_CHAN:0]overrun;
-
- //wires
- wire channel_ready;
- //command packet is ready if command packet is ready to be sent or data
- //packet contain enough data
- assign channel_ready = (rd_select == NUM_CHAN) ? (chan_usedw > 0 &&
rx_WR_done) :
- (chan_usedw >= `STDPAYLOAD);
- wire [8:0] channel_payload;
- //payload of data packets are always 504 and the payload of command packets
- //varies
- assign channel_payload = (rd_select == NUM_CHAN) ? (chan_usedw[8:0]) :
`STDPAYLOAD;
- wire [4:0] channel_name;
- //channel name is the index of the channel except for command channel where
- //index is 5'h1f
- assign channel_name = (rd_select == NUM_CHAN) ? (5'h1f) : (rd_select);
-
- assign debugbus = {1'd0, rxclk, state, rd_select[0], have_space,
channel_ready};
- always @(posedge rxclk)
- begin
- if (reset)
- begin
- state <= 0;
- payload_read <= 0;
- overrun <= 0;
- rd_select <= 0;
- WR <= 0;
- rx_WR_enabled <= 1;
- end
- else case (state)
- `IDLE:
- begin
- chan_rdreq <= 0;
- //check if a packet is ready to be sent
- if (have_space & channel_ready)
- begin
- state <= `HEADER1;
- if (rd_select == NUM_CHAN)
- begin
- rx_WR_enabled <= 0;
- end
- end
- if (~have_space & channel_ready)
- begin
- overrun[rd_select] <= 1;
- end
- if (have_space & ~channel_ready)
- begin
- rd_select <= (rd_select == NUM_CHAN) ? 0: (rd_select +
4'd1);
- end
- end
- `HEADER1:
- begin
- fifodata[`PAYLOAD_LEN] <= channel_payload;
- fifodata[`TAG] <= 0;
- fifodata[`MBZ] <= 0;
- payload_len <= channel_payload;
- payload_read <= 0;
- WR <= 1;
- state <= `HEADER2;
- end
- `HEADER2:
- begin
- fifodata[`CHAN] <= channel_name;
- fifodata[`RSSI] <= rssi;
- fifodata[`BURST] <= 0;
- fifodata[`DROPPED] <= 0;
- fifodata[`UNDERRUN] <= chan_underrun;
- fifodata[`OVERRUN] <= overrun[rd_select];
- state <= `TIMESTAMP1;
+ assign debugbus = {state, chan_empty[0], underrun[0], check_next[0],
+ have_space, rd_select[0]};
+ assign chan_used = chan_usedw[8:0];
+ assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
+ ((rd_select[0]) ?
rssi_1:rssi_0);
+ assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next -
4'd1});
+ assign ready_to_send = (chan_used == 9'd504) ||
+ ((rd_select == NUM_CHAN)&&(chan_used > 0));
+
+ always @(posedge rxclk)
+ begin
+ if (reset)
+ begin
+ overrun <= 0;
+ WR <= 0;
+ rd_select <= 0;
+ chan_rdreq <= 0;
+ tstamp_complete <= 0;
+ check_next <= 0;
+ state <= `IDLE;
+ end
+ else case (state)
+ `IDLE: begin
+ chan_rdreq <= #1 0;
+ //check if the channel is full
+ if(~chan_empty[check_next])
+ begin
+ if (have_space)
+ begin
+ //transmit if the usb buffer have space
+ //check if we should send
+ if (ready_to_send)
+ state <= #1 `HEADER1;
+
+ overrun[check_next] <= 0;
+ end
+ else
+ begin
+ state <= #1 `IDLE;
+ overrun[check_next] <= 1;
+ end
+ rd_select <= #1 check_next;
+ end
+ check_next <= #1 (check_next == channels ? 4'd0 : check_next +
4'd1);
end
-
- `TIMESTAMP1:
- begin
- fifodata <= adctime[15:0];
- state <= `TIMESTAMP2;
+
+ `HEADER1: begin
+ fifodata[`PAYLOAD_LEN] <= #1 9'd504;
+ payload_len <= #1 9'd504;
+ fifodata[`TAG] <= #1 0;
+ fifodata[`MBZ] <= #1 0;
+ WR <= #1 1;
+
+ state <= #1 `HEADER2;
+ read_length <= #1 0;
end
- `TIMESTAMP2:
- begin
- fifodata <= adctime[31:16];
- state <= `FORWARD;
- chan_rdreq <= 1;
+
+ `HEADER2: begin
+ fifodata[`CHAN] <= #1 true_channel;
+ fifodata[`RSSI] <= #1 true_rssi[5:0];
+ fifodata[`BURST] <= #1 0;
+ fifodata[`DROPPED] <= #1 0;
+ fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 :
underrun[true_channel];
+ fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 :
overrun[true_channel];
+ state <= #1 `TIMESTAMP;
end
- `FORWARD:
- begin
- if (payload_read >= `STDPAYLOAD)
- begin
- WR <= 0;
- state <= `IDLE;
- rx_WR_enabled <= 1;
- end
- else
- begin
- if (payload_len == payload_read + 9'd2)
- begin
- chan_rdreq <= 0;
- end
- payload_read <= payload_read + 9'd2;
- fifodata <= chan_fifodata;
- end
+
+ `TIMESTAMP: begin
+ fifodata <= #1 (tstamp_complete ? adctime[31:16] :
adctime[15:0]);
+ tstamp_complete <= #1 ~tstamp_complete;
+
+ if (~tstamp_complete)
+ chan_rdreq <= #1 1;
+
+ state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
end
- default:
- begin
- state <= `IDLE;
+
+ `FORWARD: begin
+ read_length <= #1 read_length + 9'd2;
+ fifodata <= #1 (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
+
+ if (read_length >= `MAXPAYLOAD)
+ begin
+ WR <= #1 0;
+ state <= #1 `IDLE;
+ chan_rdreq <= #1 0;
+ end
+ else if (read_length == payload_len - 4)
+ chan_rdreq <= #1 0;
end
- endcase
+
+ default: begin
+ //handling error state
+ state <= `IDLE;
+ end
+ endcase
end
endmodule
+
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-12-06 08:04:21 UTC (rev 7077)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-12-06 22:26:28 UTC (rev 7078)
@@ -104,7 +104,7 @@
assign rssi_wait = out[2];
assign strobe_wr = strobe;
- always @(posedge clk)
+ always @(*)
if (reset | ~enable[1])
begin
strobe <= 0;
@@ -133,7 +133,7 @@
end
end
- //register declarations
+//register declarations
setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));
setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
@@ -150,4 +150,4 @@
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));
-endmodule
\ No newline at end of file
+endmodule
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-12-06 08:04:21 UTC (rev 7077)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-12-06 22:26:28 UTC (rev 7078)
@@ -1,120 +1,178 @@
+//`include "../../firmware/include/fpga_regs_common.v"
+//`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer_inband
- ( input usbclk, input bus_reset, input reset, input reset_regs,
- output [15:0] usbdata, input RD, output wire have_pkt_rdy,
- output reg rx_overrun, input wire [3:0] channels,
- input wire [15:0] ch_0, input wire [15:0] ch_1, input wire [15:0] ch_2,
- input wire [15:0] ch_3, input wire [15:0] ch_4, input wire [15:0] ch_5,
- input wire [15:0] ch_6, input wire [15:0] ch_7, input rxclk, input
rxstrobe,
- input clear_status, output wire [15:0] debugbus,
- input rx_WR, input [15:0] rx_databus, input rx_WR_done, output wire
rx_WR_enabled,
- input wire [31:0] rssi_0, input wire [31:0] rssi_1,
- input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- input wire [1:0] tx_underrun);
-
- parameter NUM_CHAN = 1;
- genvar i ;
- wire [3:0] rd_select;
+ ( input usbclk,
+ input bus_reset,
+ input reset, // DSP side reset (used here), do not reset registers
+ input reset_regs, //Only reset registers
+ output [15:0] usbdata,
+ input RD,
+ output wire have_pkt_rdy,
+ output reg rx_overrun,
+ input wire [3:0] channels,
+ input wire [15:0] ch_0,
+ input wire [15:0] ch_1,
+ input wire [15:0] ch_2,
+ input wire [15:0] ch_3,
+ input wire [15:0] ch_4,
+ input wire [15:0] ch_5,
+ input wire [15:0] ch_6,
+ input wire [15:0] ch_7,
+ input rxclk,
+ input rxstrobe,
+ input clear_status,
+ input [6:0] serial_addr,
+ input [31:0] serial_data,
+ input serial_strobe,
+ output wire [15:0] debugbus,
+
+ //Connection with tx_inband
+ input rx_WR,
+ input [15:0] rx_databus,
+ input rx_WR_done,
+ output reg rx_WR_enabled,
+ //signal strength
+ input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+ input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+ input wire [1:0] tx_underrun
+ );
- // FX2 Bug Fix
- reg [8:0] read_count;
- always @(negedge usbclk)
- if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
- else
- read_count <= #1 RD ? read_count : 9'b0;
+ parameter NUM_CHAN = 1;
+ genvar i ;
+
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
- // Time counter
- reg [31:0] adctime;
- always @(posedge rxclk)
- if (reset)
- adctime <= 0;
- else if (rxstrobe)
- adctime <= adctime + 1;
+ // Time counter
+ reg [31:0] adctime;
+ always @(posedge rxclk)
+ if (reset)
+ adctime <= 0;
+ else if (rxstrobe)
+ adctime <= adctime + 1;
+
+ // USB side fifo
+ wire [11:0] rdusedw;
+ wire [11:0] wrusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
- //usb side fifo
- wire [11:0] wrusedw;
- wire [11:0] rdusedw;
- wire [15:0] fifodata;
- wire WR;
- wire have_space;
+ fifo_4kx16_dc rx_usb_fifo (
+ .aclr ( reset ),
+ .data ( fifodata ),
+ .rdclk ( ~usbclk ),
+ .rdreq ( RD & ~read_count[8] ),
+ .wrclk ( rxclk ),
+ .wrreq ( WR ),
+ .q ( usbdata ),
+ .rdempty ( ),
+ .rdusedw ( rdusedw ),
+ .wrfull ( ),
+ .wrusedw ( wrusedw ) );
+
+ assign have_pkt_rdy = (rdusedw >= 12'd256);
+ assign have_space = (wrusedw < 12'd760);
+
+ // Rx side fifos
+ wire chan_rdreq;
+ wire [15:0] chan_fifodata;
+ wire [9:0] chan_usedw;
+ wire [NUM_CHAN:0] chan_empty;
+ wire [3:0] rd_select;
+ wire [NUM_CHAN:0] rx_full;
+
+ packet_builder #(NUM_CHAN) rx_pkt_builer (
+ .rxclk ( rxclk ),
+ .reset ( reset ),
+ .adctime ( adctime ),
+ .channels ( 4'd1 ), //need to be tested and changed to channels
+ .chan_rdreq ( chan_rdreq ),
+ .chan_fifodata ( chan_fifodata ),
+ .chan_empty ( chan_empty ),
+ .rd_select ( rd_select ),
+ .chan_usedw ( chan_usedw ),
+ .WR ( WR ),
+ .fifodata ( fifodata ),
+ .have_space ( have_space ),
+ .rssi_0(rssi_0), .rssi_1(rssi_1),
+ .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
+ .underrun(tx_underrun));
+
+ // Detect overrun
- fifo_4kx16_dc rx_usb_fifo
- (.aclr(reset), .data(fifodata), .rdclk(~usbclk), .rdreq(RD & ~read_count[8]),
- .wrclk(rxclk), .wrreq(WR), .q(usbdata), .wrusedw(wrusedw),
.rdusedw(rdusedw));
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rx_full[0])
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
- assign have_space = (wrusedw < 12'd760);
- assign have_pkt_rdy = (rdusedw >= 12'd512);
+
+ // TODO write this genericly
+ wire [15:0]ch[NUM_CHAN:0];
+ assign ch[0] = ch_0;
+
+ wire cmd_empty;
- //need to change the parameters later to make this more robust
- wire [31:0] rssi;
- assign rssi = rd_select[0] ? rssi_1: rssi_0;
- wire chan_underrun;
- assign chan_underrun = rd_select[0] ? tx_underrun[1] : tx_underrun[0];
+ always @(posedge rxclk)
+ if(reset)
+ rx_WR_enabled <= 1;
+ else if(cmd_empty)
+ rx_WR_enabled <= 1;
+ else if(rx_WR_done)
+ rx_WR_enabled <= 0;
- wire [7:0] pb_debug;
- wire [31:0] chan_fifodata;
- wire [9:0] chan_usedw;
- wire chan_rdreq;
+ wire [15:0] dataout [0:NUM_CHAN];
+ wire [9:0] usedw [0:NUM_CHAN];
+ wire empty[0:NUM_CHAN];
+
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ begin : generate_channel_fifos
+
+ wire rdreq;
- packet_builder #(NUM_CHAN) rx_pkt_builder
- (.rxclk(rxclk), .reset(reset), .adctime(adctime),
- .chan_fifodata(chan_fifodata), .chan_usedw(chan_usedw),
- .rd_select(rd_select), .chan_rdreq(chan_rdreq), .WR(WR),
- .fifodata(fifodata), .have_space(have_space),
- .rssi(rssi[5:0]), .debugbus(pb_debug), .chan_underrun(chan_underrun),
- .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled));
+ assign rdreq = (rd_select == i) & chan_rdreq;
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(usedw[0]>=10'd1008)
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
+ fifo_1kx16 rx_chan_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( ch[i] ),
+ .rdreq ( rdreq ),
+ .wrreq ( ~rx_full[i] & rxstrobe),
+ .empty (empty[i]),
+ .full (rx_full[i]),
+ .q ( dataout[i]),
+ .usedw ( usedw[i]),
+ .almost_empty(chan_empty[i])
+ );
+ end
+ endgenerate
+
+ wire [7:0] debug;
+
+ fifo_1kx16 rx_cmd_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( rx_databus ),
+ .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
+ .wrreq ( rx_WR & rx_WR_enabled),
+ .empty ( cmd_empty),
+ .full ( rx_full[NUM_CHAN] ),
+ .q ( dataout[NUM_CHAN]),
+ .usedw ( usedw[NUM_CHAN] )
+ );
+
+ assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+ assign chan_fifodata = dataout[rd_select];
+ assign chan_usedw = usedw[rd_select];
- wire [15:0]ch[7:0];
- assign ch[0] = ch_0;
- assign ch[1] = ch_1;
- assign ch[2] = ch_2;
- assign ch[3] = ch_3;
- assign ch[4] = ch_4;
- assign ch[5] = ch_5;
- assign ch[6] = ch_6;
- assign ch[7] = ch_7;
-
- wire [15:0] dataout [0:NUM_CHAN];
- wire [9:0] usedw [0:NUM_CHAN];
-
- generate for (i = 0; i < NUM_CHAN; i = i + 1)
- begin : generate_channel_fifos
- wire rdreq;
-
- assign rdreq = (rd_select == i) & chan_rdreq;
-
- fifo_1kx16 rx_chan_fifo
- (.aclr(reset), .clock(rxclk), .data(ch[i]), .rdreq(rdreq),
- .wrreq((usedw[i]<=10'd1008) & rxstrobe), .q(dataout[i]),
- .usedw(usedw[i]));
-
- end
- endgenerate
-
- fifo_1kx16 rx_cmd_fifo
- (.aclr(reset), .clock(rxclk), .data(rx_databus),
- .rdreq((rd_select == NUM_CHAN) & chan_rdreq),
- .wrreq(rx_WR & rx_WR_enabled), .q(dataout[NUM_CHAN]),
- .usedw(usedw[NUM_CHAN]));
-
- assign chan_fifodata = dataout[rd_select];
- assign chan_usedw = usedw[rd_select];
- wire [9:0] tmp;
- assign tmp = usedw[0];
- assign debugbus = {usbclk, rxclk, tmp[9:2], have_space, have_pkt_rdy,
- (usedw[0]<=10'd1008) , rxstrobe, chan_rdreq,
rd_select[0]};
-
endmodule
-
-
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-12-06 08:04:21 UTC (rev 7077)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-12-06 22:26:28 UTC (rev 7078)
@@ -13,7 +13,7 @@
output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
input wire rx_WR_enabled,
//register io
- output wire reg_io_enable, output wire [31:0] reg_data_in, output wire
[6:0] reg_addr,
+ output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output
wire [6:0] reg_addr,
input wire [31:0] reg_data_out,
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0]
rssi_2,
@@ -33,8 +33,8 @@
/* These will eventually be external register */
reg [31:0] adc_time ;
- wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
- wire [31:0] rssi [3:0];
+ wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
+ wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
assign rssi[2] = rssi_2;
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16.bsf
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16.bsf
2007-12-06 08:04:21 UTC (rev 7077)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16.bsf
2007-12-06 22:26:28 UTC (rev 7078)
@@ -95,7 +95,7 @@
)
(drawing
(text "16 bits x 1024 words" (rect 58 132 144 144)(font "Arial"
))
- (text "almost_empty < 126" (rect 58 122 144 134)(font "Arial" ))
+ (text "almost_empty < 504" (rect 58 122 144 134)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 144)(line_width 1))
(line (pt 144 144)(pt 16 144)(line_width 1))
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16.v
2007-12-06 08:04:21 UTC (rev 7077)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16.v
2007-12-06 22:26:28 UTC (rev 7078)
@@ -86,7 +86,7 @@
);
defparam
scfifo_component.add_ram_output_register = "OFF",
- scfifo_component.almost_empty_value = 126,
+ scfifo_component.almost_empty_value = 504,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
@@ -105,7 +105,7 @@
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
@@ -133,7 +133,7 @@
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126"
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16_bb.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16_bb.v
2007-12-06 08:04:21 UTC (rev 7077)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/megacells/fifo_1kx16_bb.v
2007-12-06 22:26:28 UTC (rev 7078)
@@ -57,7 +57,7 @@
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
-// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "126"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
@@ -85,7 +85,7 @@
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "126"
+// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
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