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[Commit-gnuradio] r7012 - usrp2/trunk/fpga/eth/rtl/verilog
From: |
matt |
Subject: |
[Commit-gnuradio] r7012 - usrp2/trunk/fpga/eth/rtl/verilog |
Date: |
Wed, 21 Nov 2007 01:32:20 -0700 (MST) |
Author: matt
Date: 2007-11-21 01:32:16 -0700 (Wed, 21 Nov 2007)
New Revision: 7012
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v
Log:
remove remnants of the old bus
Modified: usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v 2007-11-21 03:50:59 UTC (rev
7011)
+++ usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v 2007-11-21 08:32:16 UTC (rev
7012)
@@ -10,14 +10,6 @@
output reg [15:0] DAT_O, // Read data
output reg ACK_O, // Acknowledge output � single high pulse
-// input Reset,
-// input Clk_reg,
-// input CSB,
-// input WRB,
-// input [15:0] CD_in,
-// output reg [15:0] CD_out,
-// input [7:0] CA,
-
// Tx host interface
output [4:0] Tx_Hwmark,
output [4:0] Tx_Lwmark,
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