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[Commit-gnuradio] r7005 - in usrp2/trunk/fpga/eth/rtl/verilog: MAC_rx MA
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r7005 - in usrp2/trunk/fpga/eth/rtl/verilog: MAC_rx MAC_tx RMON |
|
Date: |
Mon, 19 Nov 2007 20:54:14 -0700 (MST) |
Author: matt
Date: 2007-11-19 20:54:09 -0700 (Mon, 19 Nov 2007)
New Revision: 7005
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v
usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v
usrp2/trunk/fpga/eth/rtl/verilog/RMON/RMON_dpram.v
Log:
mac address insertion and checking no longer waste a block ram. Functionality
not checked yet, but these are optional fetures anyway
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v 2007-11-19
21:44:41 UTC (rev 7004)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v 2007-11-20
03:54:09 UTC (rev 7005)
@@ -1,40 +1,40 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// MAC_rx_add_chk.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode/////
-//// ////
-//// Author(s): ////
-//// - Jon Gao (address@hidden) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
+// ////////////////////////////////////////////////////////////////////
+// // ////
+// // MAC_rx_add_chk.v ////
+// // ////
+// // This file is part of the Ethernet IP core project ////
+// // http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode/////
+// // ////
+// // Author(s): ////
+// // - Jon Gao (address@hidden) ////
+// // ////
+// // ////
+// ////////////////////////////////////////////////////////////////////
+// // ////
+// // Copyright (C) 2001 Authors ////
+// // ////
+// // This source file may be used and distributed without ////
+// // restriction provided that this copyright statement is not ////
+// // removed from the file and that any derivative work contains ////
+// // the original copyright notice and the associated disclaimer. ////
+// // ////
+// // This source file is free software; you can redistribute it ////
+// // and/or modify it under the terms of the GNU Lesser General ////
+// // Public License as published by the Free Software Foundation; ////
+// // either version 2.1 of the License, or (at your option) any ////
+// // later version. ////
+// // ////
+// // This source is distributed in the hope that it will be ////
+// // useful, but WITHOUT ANY WARRANTY; without even the implied ////
+// // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+// // PURPOSE. See the GNU Lesser General Public License for more ////
+// // details. ////
+// // ////
+// // You should have received a copy of the GNU Lesser General ////
+// // Public License along with this source; if not, download it ////
+// // from http://www.opencores.org/lgpl.shtml ////
+// // ////
+// ////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
@@ -50,111 +50,123 @@
// no message
//
-module MAC_rx_add_chk (
-Reset ,
-Clk ,
-Init ,
-data ,
-MAC_add_en ,
-MAC_rx_add_chk_err ,
-//From CPU
-MAC_rx_add_chk_en ,
-MAC_add_prom_data ,
-MAC_add_prom_add ,
-MAC_add_prom_wr
+module MAC_rx_add_chk
+ (Reset ,
+ Clk ,
+ Init ,
+ data ,
+ MAC_add_en ,
+ MAC_rx_add_chk_err ,
+ //From CPU
+ MAC_rx_add_chk_en ,
+ MAC_add_prom_data ,
+ MAC_add_prom_add ,
+ MAC_add_prom_wr
+ );
-);
-input Reset ;
-input Clk ;
-input Init ;
-input [7:0] data ;
-input MAC_add_en ;
-output MAC_rx_add_chk_err ;
- //From CPU
-input MAC_rx_add_chk_en ;
-input [7:0] MAC_add_prom_data ;
-input [2:0] MAC_add_prom_add ;
-input MAC_add_prom_wr ;
+ input Reset ;
+ input Clk ;
+ input Init ;
+ input [7:0] data ;
+ input MAC_add_en ;
+ output MAC_rx_add_chk_err ;
+ //From CPU
+ input MAC_rx_add_chk_en ;
+ input [7:0] MAC_add_prom_data ;
+ input [2:0] MAC_add_prom_add ;
+ input MAC_add_prom_wr ;
+
+ //
******************************************************************************
+ // internal signals
+ //
******************************************************************************
+ reg [2:0] addr_rd;
+ wire [2:0] addr_wr;
+ wire [7:0] din;
+ //wire [7:0] dout;
+ reg [7:0] dout;
+ wire wr_en;
+
+ reg MAC_rx_add_chk_err;
+ reg MAC_add_prom_wr_dl1;
+ reg MAC_add_prom_wr_dl2;
+ reg [7:0] data_dl1 ;
+ reg MAC_add_en_dl1 ;
-//******************************************************************************
-//internal signals
-//******************************************************************************
-reg [2:0] addr_rd;
-wire[2:0] addr_wr;
-wire[7:0] din;
-wire[7:0] dout;
-wire wr_en;
+ //
******************************************************************************
+ // write data from cpu to prom
+ //
******************************************************************************
+ always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ begin
+ data_dl1 <=0;
+ MAC_add_en_dl1 <=0;
+ end
+ else
+ begin
+ data_dl1 <=data;
+ MAC_add_en_dl1 <=MAC_add_en;
+ end
+
+ always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ begin
+ MAC_add_prom_wr_dl1 <=0;
+ MAC_add_prom_wr_dl2 <=0;
+ end
+ else
+ begin
+ MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;
+ MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;
+ end
+
+ assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
+ assign addr_wr =MAC_add_prom_add;
+ assign din =MAC_add_prom_data;
+
+ //
******************************************************************************
+ // mac add verify
+ //
******************************************************************************
+ always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ addr_rd <=0;
+ else if (Init)
+ addr_rd <=0;
+ else if (MAC_add_en)
+ addr_rd <=addr_rd + 1;
+
+ always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ MAC_rx_add_chk_err <=0;
+ else if (Init)
+ MAC_rx_add_chk_err <=0;
+ else if (MAC_rx_add_chk_en && MAC_add_en_dl1 && (dout!=data_dl1) )
+ MAC_rx_add_chk_err <=1;
+
+
+ //
******************************************************************************
+ // a port for read ,b port for write .
+ //
******************************************************************************
-reg MAC_rx_add_chk_err;
-reg MAC_add_prom_wr_dl1;
-reg MAC_add_prom_wr_dl2;
-reg [7:0] data_dl1 ;
-reg MAC_add_en_dl1 ;
-//******************************************************************************
-//write data from cpu to prom
-//******************************************************************************
-always @ (posedge Clk or posedge Reset)
- if (Reset)
- begin
- data_dl1 <=0;
- MAC_add_en_dl1 <=0;
- end
- else
- begin
- data_dl1 <=data;
- MAC_add_en_dl1 <=MAC_add_en;
- end
+ reg [7:0] address_ram [0:7];
+ always @(posedge Clk)
+ if(wr_en)
+ address_ram[addr_wr] <= din;
+
+ always @(posedge Clk)
+ dout <= address_ram[addr_rd];
-always @ (posedge Clk or posedge Reset)
- if (Reset)
- begin
- MAC_add_prom_wr_dl1 <=0;
- MAC_add_prom_wr_dl2 <=0;
- end
- else
- begin
- MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;
- MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;
- end
-
-assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
-assign addr_wr =MAC_add_prom_add;
-assign din =MAC_add_prom_data;
-
-//******************************************************************************
-//mac add verify
-//******************************************************************************
-always @ (posedge Clk or posedge Reset)
- if (Reset)
- addr_rd <=0;
- else if (Init)
- addr_rd <=0;
- else if (MAC_add_en)
- addr_rd <=addr_rd + 1;
-
-always @ (posedge Clk or posedge Reset)
- if (Reset)
- MAC_rx_add_chk_err <=0;
- else if (Init)
- MAC_rx_add_chk_err <=0;
- else if (MAC_rx_add_chk_en && MAC_add_en_dl1 && (dout!=data_dl1) )
- MAC_rx_add_chk_err <=1;
-
-
-//******************************************************************************
-//a port for read ,b port for write .
-//******************************************************************************
-duram #(8,3,"M512","DUAL_PORT") U_duram(
- .data_a ( din ),
- .data_b ( 8'b0 ),
- .wren_a ( wr_en ),
- .wren_b ( 1'b0 ),
- .address_a( addr_wr ),
- .address_b( addr_rd ),
- .clock_a ( Clk ),
- .clock_b ( Clk ),
- .q_a (),
- .q_b ( dout )
-);
-
-endmodule
+ /*
+ duram #(8,3,"M512","DUAL_PORT")
+ U_duram(.data_a ( din ),
+ .data_b ( 8'b0 ),
+ .wren_a ( wr_en ),
+ .wren_b ( 1'b0 ),
+ .address_a( addr_wr ),
+ .address_b( addr_rd ),
+ .clock_a ( Clk ),
+ .clock_b ( Clk ),
+ .q_a (),
+ .q_b ( dout )
+ );
+ */
+endmodule // MAC_rx_add_chk
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v 2007-11-19
21:44:41 UTC (rev 7004)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v 2007-11-20
03:54:09 UTC (rev 7005)
@@ -1,40 +1,40 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// MAC_tx_addr_add.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode/////
-//// ////
-//// Author(s): ////
-//// - Jon Gao (address@hidden) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
+// ////////////////////////////////////////////////////////////////////
+// // ////
+// // MAC_tx_addr_add.v ////
+// // ////
+// // This file is part of the Ethernet IP core project ////
+// // http://www.opencores.org/projects.cgi/wr_en/ethernet_tri_mode/////
+// // ////
+// // Author(s): ////
+// // - Jon Gao (address@hidden) ////
+// // ////
+// // ////
+// ////////////////////////////////////////////////////////////////////
+// // ////
+// // Copyright (C) 2001 Authors ////
+// // ////
+// // This source file may be used and distributed without ////
+// // restriction provided that this copyright statement is not ////
+// // removed from the file and that any derivative work contains ////
+// // the original copyright notice and the associated disclaimer. ////
+// // ////
+// // This source file is free software; you can redistribute it ////
+// // and/or modify it under the terms of the GNU Lesser General ////
+// // Public License as published by the Free Software Foundation; ////
+// // either version 2.1 of the License, or (at your option) any ////
+// // later version. ////
+// // ////
+// // This source is distributed in the hope that it will be ////
+// // useful, but WITHOUT ANY WARRANTY; without even the implied ////
+// // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+// // PURPOSE. See the GNU Lesser General Public License for more ////
+// // details. ////
+// // ////
+// // You should have received a copy of the GNU Lesser General ////
+// // Public License along with this source; if not, download it ////
+// // from http://www.opencores.org/lgpl.shtml ////
+// // ////
+// ////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
@@ -50,84 +50,93 @@
// no message
//
-module MAC_tx_addr_add (
-Reset ,
-Clk ,
-MAC_tx_addr_init ,
-MAC_tx_addr_rd ,
-MAC_tx_addr_data ,
-//CPU ,
-MAC_add_prom_data ,
-MAC_add_prom_add ,
-MAC_add_prom_wr
-);
+module MAC_tx_addr_add
+ (Reset ,
+ Clk ,
+ MAC_tx_addr_init ,
+ MAC_tx_addr_rd ,
+ MAC_tx_addr_data ,
+ //CPU ,
+ MAC_add_prom_data ,
+ MAC_add_prom_add ,
+ MAC_add_prom_wr
+ );
+
+ input Reset ;
+ input Clk ;
+ input MAC_tx_addr_rd ;
+ input MAC_tx_addr_init ;
+ output [7:0] MAC_tx_addr_data ;
+ //CPU ;
+ input [7:0] MAC_add_prom_data ;
+ input [2:0] MAC_add_prom_add ;
+ input MAC_add_prom_wr ;
+
+ //
******************************************************************************
+ // internal signals
+ //
******************************************************************************
+ reg [2:0] add_rd;
+ wire [2:0] add_wr;
+ wire [7:0] din;
+ //wire [7:0] dout;
+ reg [7:0] dout;
+ wire wr_en;
+ reg MAC_add_prom_wr_dl1;
+ reg MAC_add_prom_wr_dl2;
+ //
******************************************************************************
+ // write data from cpu to prom
+ //
******************************************************************************
+ always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ begin
+ MAC_add_prom_wr_dl1 <=0;
+ MAC_add_prom_wr_dl2 <=0;
+ end
+ else
+ begin
+ MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;
+ MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;
+ end
+
+ assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
+ assign add_wr =MAC_add_prom_add;
+ assign din =MAC_add_prom_data;
+
+ //
******************************************************************************
+ // read data from cpu to prom
+ //
******************************************************************************
+ always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ add_rd <=0;
+ else if (MAC_tx_addr_init)
+ add_rd <=0;
+ else if (MAC_tx_addr_rd)
+ add_rd <=add_rd + 1;
+ assign MAC_tx_addr_data=dout;
+ //
******************************************************************************
+ // b port for read ,a port for write .
+ //
******************************************************************************
+
+ reg [7:0] address_ram [0:7];
+ always @(posedge Clk)
+ if(wr_en)
+ address_ram[add_wr] <= din;
-input Reset ;
-input Clk ;
-input MAC_tx_addr_rd ;
-input MAC_tx_addr_init ;
-output [7:0] MAC_tx_addr_data ;
- //CPU ;
-input [7:0] MAC_add_prom_data ;
-input [2:0] MAC_add_prom_add ;
-input MAC_add_prom_wr ;
+ always @(posedge Clk)
+ dout <= address_ram[add_rd];
-//******************************************************************************
-//internal signals
-//******************************************************************************
-reg [2:0] add_rd;
-wire[2:0] add_wr;
-wire[7:0] din;
-wire[7:0] dout;
-wire wr_en;
-reg MAC_add_prom_wr_dl1;
-reg MAC_add_prom_wr_dl2;
-//******************************************************************************
-//write data from cpu to prom
-//******************************************************************************
-always @ (posedge Clk or posedge Reset)
- if (Reset)
- begin
- MAC_add_prom_wr_dl1 <=0;
- MAC_add_prom_wr_dl2 <=0;
- end
- else
- begin
- MAC_add_prom_wr_dl1 <=MAC_add_prom_wr;
- MAC_add_prom_wr_dl2 <=MAC_add_prom_wr_dl1;
- end
-
-assign wr_en =MAC_add_prom_wr_dl1&!MAC_add_prom_wr_dl2;
-assign add_wr =MAC_add_prom_add;
-assign din =MAC_add_prom_data;
-
-//******************************************************************************
-//read data from cpu to prom
-//******************************************************************************
-always @ (posedge Clk or posedge Reset)
- if (Reset)
- add_rd <=0;
- else if (MAC_tx_addr_init)
- add_rd <=0;
- else if (MAC_tx_addr_rd)
- add_rd <=add_rd + 1;
-assign MAC_tx_addr_data=dout;
-//******************************************************************************
-//b port for read ,a port for write .
-//******************************************************************************
-duram #(8,3,"M512","DUAL_PORT") U_duram(
- .data_a ( din ),
- .data_b ( 8'b0 ),
- .wren_a ( wr_en ),
- .wren_b ( 1'b0 ),
- .address_a ( add_wr ),
- .address_b ( add_rd ),
- .clock_a ( Clk ),
- .clock_b ( Clk ),
- .q_a (),
- .q_b ( dout )
-);
-
-
-endmodule
-
+ /*
+ duram #(8,3,"M512","DUAL_PORT")
+ U_duram(.data_a ( din ),
+ .data_b ( 8'b0 ),
+ .wren_a ( wr_en ),
+ .wren_b ( 1'b0 ),
+ .address_a ( add_wr ),
+ .address_b ( add_rd ),
+ .clock_a ( Clk ),
+ .clock_b ( Clk ),
+ .q_a (),
+ .q_b ( dout )
+ );
+ */
+endmodule // MAC_tx_addr_add
Modified: usrp2/trunk/fpga/eth/rtl/verilog/RMON/RMON_dpram.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/RMON/RMON_dpram.v 2007-11-19 21:44:41 UTC
(rev 7004)
+++ usrp2/trunk/fpga/eth/rtl/verilog/RMON/RMON_dpram.v 2007-11-20 03:54:09 UTC
(rev 7005)
@@ -1,51 +1,52 @@
-`timescale 1 ns / 1 ns
-module RMON_dpram(
-Reset ,
-Clk ,
-//port-a for Rmon
-Addra,
-Dina,
-Douta,
-Wea,
-//port-b for CPU
-Addrb,
-Doutb
-);
+module RMON_dpram
+ (Reset ,
+ Clk ,
+ //port-a for Rmon
+ Addra,
+ Dina,
+ Douta,
+ Wea,
+ //port-b for CPU
+ Addrb,
+ Doutb
+ );
-input Reset ;
-input Clk ;
- //port-a for Rmon
-input [5:0] Addra;
-input [31:0] Dina;
-output [31:0] Douta;
-input Wea;
- //port-b for CPU
-input [5:0] Addrb;
-output [31:0] Doutb;
-//******************************************************************************
-//internal signals
-//******************************************************************************
+ input Reset ;
+ input Clk ;
+ //port-a for Rmon
+ input [5:0] Addra;
+ input [31:0] Dina;
+ output [31:0] Douta;
+ input Wea;
+ //port-b for CPU
+ input [5:0] Addrb;
+ output [31:0] Doutb;
-wire Clka;
-wire Clkb;
-assign Clka=Clk;
-// This delay is solely to prevent countless warnings about
-// simultaneous read & write to the dual port RAM
-assign #1 Clkb=Clk;
+ //
******************************************************************************
+ // internal signals
+ //
******************************************************************************
+
+ wire Clka;
+ wire Clkb;
+ assign Clka=Clk;
+ // This delay is solely to prevent countless warnings about
+ // simultaneous read & write to the dual port RAM
+ assign #1 Clkb=Clk;
-//******************************************************************************
+ //
******************************************************************************
+
+ duram #(32,6,"M4K")
+ U_duram(.data_a (Dina ),
+ .data_b (32'b0 ),
+ .wren_a (Wea ),
+ .wren_b (1'b0 ),
+ .address_a (Addra ),
+ .address_b (Addrb ),
+ .clock_a (Clka ),
+ .clock_b (Clkb ),
+ .q_a (Douta ),
+ .q_b (Doutb ));
+
+endmodule // RMON_dpram
-duram #(32,6,"M4K") U_duram(
-.data_a (Dina ),
-.data_b (32'b0 ),
-.wren_a (Wea ),
-.wren_b (1'b0 ),
-.address_a (Addra ),
-.address_b (Addrb ),
-.clock_a (Clka ),
-.clock_b (Clkb ),
-.q_a (Douta ),
-.q_b (Doutb ));
-
-endmodule
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