[Commit-gnuradio] r6998 - in usrp2/trunk: firmware/lib fpga/sdr_lib

[matt]

Author: matt
Date: 2007-11-19 00:29:07 -0700 (Mon, 19 Nov 2007)
New Revision: 6998

Modified:
   usrp2/trunk/firmware/lib/memory_map.h
   usrp2/trunk/fpga/sdr_lib/rx_control.v
Log:
added clear_state to get out of overrun


Modified: usrp2/trunk/firmware/lib/memory_map.h
===================================================================
--- usrp2/trunk/firmware/lib/memory_map.h       2007-11-19 07:27:56 UTC (rev 
6997)
+++ usrp2/trunk/firmware/lib/memory_map.h       2007-11-19 07:29:07 UTC (rev 
6998)
@@ -316,6 +316,7 @@
   volatile int          decim_rate;
   volatile int          rx_time;
   volatile int          rx_command;
+  volatile int          clear_state;
 } dsp_rx_regs_t;
   
 #define dsp_rx_regs ((dsp_rx_regs_t *) DSP_RX_BASE)

Modified: usrp2/trunk/fpga/sdr_lib/rx_control.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/rx_control.v       2007-11-19 07:27:56 UTC (rev 
6997)
+++ usrp2/trunk/fpga/sdr_lib/rx_control.v       2007-11-19 07:29:07 UTC (rev 
6998)
@@ -24,7 +24,7 @@
      input strobe
      );
 
-   wire [31:0] new_time, new_command;
+   wire [31:0] new_time, new_command, clear_overrun;
    wire        sc_pre1, store_command;
    setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -34,6 +34,10 @@
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(new_command),.changed());
 
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+5)) sr_5
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_overrun));
+
    reg                sc_pre2;
    always @(posedge clk)
      sc_pre2 <= sc_pre1;
@@ -146,7 +150,8 @@
                    lines_left_frame <= lines_left_frame - 1;
               end // else: !if(full)
         IBS_OVERRUN :
-          ;
+          if(clear_overrun)
+            IBS_STATE <= IBS_IDLE;
        endcase // case(ibs_state)
    
    assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {1'b1,1'b0,master_time} :