[Commit-gnuradio] r6992 - in usrp2/trunk: firmware/lib fpga/control_lib fpga/top/u2_basic

[matt]

Author: matt
Date: 2007-11-18 21:07:26 -0700 (Sun, 18 Nov 2007)
New Revision: 6992

Added:
   usrp2/trunk/fpga/control_lib/atr_controller.v
Modified:
   usrp2/trunk/firmware/lib/memory_map.h
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
Auto TR switching, easily extensible


Modified: usrp2/trunk/firmware/lib/memory_map.h
===================================================================
--- usrp2/trunk/firmware/lib/memory_map.h       2007-11-18 20:13:46 UTC (rev 
6991)
+++ usrp2/trunk/firmware/lib/memory_map.h       2007-11-19 04:07:26 UTC (rev 
6992)
@@ -377,4 +377,11 @@
 
 #define uart_regs ((wb16550_reg_t *) UART_BASE)
 
+///////////////////////////////////////////////////
+// ATR Controller, Slave 11
+
+#define ATR_BASE  0xF400
+
+#define atr_regs ((int *) ATR_BASE)
+
 #endif

Added: usrp2/trunk/fpga/control_lib/atr_controller.v
===================================================================
--- usrp2/trunk/fpga/control_lib/atr_controller.v                               
(rev 0)
+++ usrp2/trunk/fpga/control_lib/atr_controller.v       2007-11-19 04:07:26 UTC 
(rev 6992)
@@ -0,0 +1,45 @@
+
+// Automatic transmit/receive switching of control pins to daughterboards
+// Store everything in registers for now, but could use a RAM for more
+// complex state machines in the future
+
+module atr_controller
+  (input clk_i, input rst_i,
+   input [3:0] adr_i, input [31:0] dat_i, output [31:0] dat_o,
+   input we_i, input stb_i, input cyc_i, output reg ack_o,
+   input run_rx, input run_tx, output [31:0] ctrl_lines);
+   
+   reg [3:0] state;
+   reg [31:0] atr_ram [0:15];  // DP distributed RAM
+
+   // WB Interface
+   always @(posedge clk_i)
+     if(we_i & stb_i & cyc_i)
+       atr_ram[adr_i] <= dat_i;
+
+   assign     dat_o = atr_ram[adr_i];
+   always @(posedge clk_i)
+     ack_o <= stb_i & cyc_i & ~ack_o;
+
+   // Control side of DP RAM
+   assign     ctrl_lines = atr_ram[state];
+
+   // Put a more complex state machine with time delays and multiple states 
here
+   //  if daughterboard requires more complex sequencing
+   localparam ATR_IDLE = 4'd0;
+   localparam ATR_TX = 4'd1;
+   localparam ATR_RX = 4'd2;
+   localparam ATR_FULL_DUPLEX = 4'd3;
+   
+   always @(posedge clk_i)
+     if(rst_i)
+       state <= ATR_IDLE;
+     else
+       case ({run_rx,run_tx})
+        2'b00 : state <= ATR_IDLE;
+        2'b01 : state <= ATR_TX;
+        2'b10 : state <= ATR_RX;
+        2'b11 : state <= ATR_FULL_DUPLEX;
+       endcase // case({run_rx,run_tx})
+   
+endmodule // atr_controller

Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-11-18 20:13:46 UTC (rev 
6991)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-11-19 04:07:26 UTC (rev 
6992)
@@ -136,7 +136,8 @@
    wire [31:0]         debug_gpio_0, debug_gpio_1;
    wire [31:0]         debug_wb, debug_txmacfifo_in, debug_txmacfifo_out, 
debug_bufpool, debug_bufpool2;
    wire [15:0]         debug_gmii_1, debug_gmii_2;
-
+   wire [31:0]         atr_lines;
+   
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
@@ -146,21 +147,21 @@
    wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
    wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, 
s2_dat_i, s3_dat_i,
                 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, 
s6_dat_i, s7_dat_i,
-                s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i;
-   wire [aw-1:0] m0_adr, m1_adr, 
s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr;
-   wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, 
s5_sel, s6_sel, s7_sel, s8_sel, s9_sel, s10_sel;
-   wire         m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, 
s5_ack, s6_ack, s7_ack, s8_ack, s9_ack, s10_ack;
-   wire         m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, 
s5_stb, s6_stb, s7_stb, s8_stb, s9_stb, s10_stb;
-   wire         m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, 
s5_cyc, s6_cyc, s7_cyc, s8_cyc, s9_cyc, s10_cyc;
-   wire         m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, 
s5_err, s6_err, s7_err, s8_err, s9_err, s10_err;
-   wire         m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, 
s5_rty, s6_rty, s7_rty, s8_rty, s9_rty, s10_rty;
-   wire         m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, 
s7_we, s8_we, s9_we, s10_we;
+                s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, 
s11_dat_i, s11_dat_o;
+   wire [aw-1:0] 
m0_adr,m1_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr;
+   wire [sw-1:0] 
m0_sel,m1_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel;
+   wire         
m0_ack,m1_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack;
+   wire         
m0_stb,m1_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb;
+   wire         
m0_cyc,m1_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc;
+   wire         
m0_err,m1_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err;
+   wire         
m0_rty,m1_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty;
+   wire         
m0_we,m1_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we;
    
    wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01),
-               
.s215_addr_w(5),.s2_addr(5'b10000),.s3_addr(5'b10010),.s4_addr(5'b10100),
-               
.s5_addr(5'b10110),.s6_addr(5'b11000),.s7_addr(5'b11010),.s8_addr(5'b11100),.s9_addr(5'b11101),
-               
.s10_addr(5'b11110),.s11_addr(5'b11111),.s12_addr(5'b11111),.s13_addr(5'b11111),
-               .s14_addr(5'b11111),.s15_addr(5'b11111),
+               
.s215_addr_w(6),.s2_addr(6'b100000),.s3_addr(6'b100100),.s4_addr(6'b101000),
+               
.s5_addr(6'b101100),.s6_addr(6'b110000),.s7_addr(6'b110100),.s8_addr(6'b111000),
+               
.s9_addr(6'b111010),.s10_addr(6'b111100),.s11_addr(6'b111101),.s12_addr(6'b111110),
+               .s13_addr(6'b111111),.s14_addr(6'b111111),.s15_addr(6'b111111),
                .dw(dw),.aw(aw),.sw(sw)) wb_1master
      (.clk_i(wb_clk),.rst_i(wb_rst),       
       
.m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
@@ -187,7 +188,8 @@
       
.s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty),
       
.s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb),
       
.s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty),
-      .s11_dat_i(0),.s11_ack_i(0),.s11_err_i(0),.s11_rty_i(0),
+      
.s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb),
+      
.s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty),
       .s12_dat_i(0),.s12_ack_i(0),.s12_err_i(0),.s12_rty_i(0),
       .s13_dat_i(0),.s13_ack_i(0),.s13_err_i(0),.s13_rty_i(0),
       .s14_dat_i(0),.s14_ack_i(0),.s14_err_i(0),.s14_rty_i(0),
@@ -330,12 +332,12 @@
    nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
                 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
                 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
-                .debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+                .debug_0(atr_lines),.debug_1(debug_gpio_1),
                 .gpio( {io_tx,io_rx} ) );
    assign       s4_err = 1'b0;
    assign       s4_rty = 1'b0;
 
-   // Buffer Pool Status #5
+   // Buffer Pool Status -- Slave #5
    wb_readback_mux buff_pool_status
      (.wb_clk_i(wb_clk),
       .wb_rst_i(wb_rst),
@@ -468,6 +470,17 @@
    assign       s10_rty = 0;
    
    // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller, Slave #11
+
+   atr_controller atr_controller
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .adr_i(s11_adr[3:0]),.dat_i(s11_dat_o),.dat_o(s11_dat_i),
+      .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack),
+      .run_rx(run_rx),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+   assign       s11_err = 0;
+   assign       s11_rty = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
    // DSP
 
    reg [13:0]   adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;