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[Commit-gnuradio] r6990 - usrp2/trunk/fpga/top/u2_basic


From: matt
Subject: [Commit-gnuradio] r6990 - usrp2/trunk/fpga/top/u2_basic
Date: Sun, 18 Nov 2007 00:35:25 -0700 (MST)

Author: matt
Date: 2007-11-18 00:35:24 -0700 (Sun, 18 Nov 2007)
New Revision: 6990

Modified:
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
put this 8-bit wishbone device on 32-bit boundary addresses b/c it doesn't 
respond to sel signals


Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-11-18 07:34:28 UTC (rev 
6989)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-11-18 07:35:24 UTC (rev 
6990)
@@ -316,7 +316,7 @@
    // I2C -- Slave #3
    i2c_master_top #(.ARST_LVL(1)) 
      i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
-         
.wb_adr_i(s3_adr[2:0]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
+         
.wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
          .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
          .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
          
.scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
@@ -346,8 +346,8 @@
       
       
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
       
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
-      
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(),.word11(),
-      .word12(),.word13(),.word14(),.word15()
+      
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
+      
.word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
       );
 
    assign       s5_err = 1'b0;
@@ -573,11 +573,11 @@
                                  Tx_mac_wa, Tx_mac_wr,rd2_read,rd2_done,
                                  rd2_error,rd2_sop,rd2_eop,status_b0[8:0]  };
    
-   assign      debug = 32'd0;
+   assign      debug = debug_bufpool2;
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
 
-   assign      debug_gpio_0 = 32'd0;
-   assign      debug_gpio_1 = 32'd0;
+   assign      debug_gpio_0 = debug_bufpool;
+   assign      debug_gpio_1 = debug_txmacfifo_in;
    
 endmodule // u2_basic





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