[Commit-gnuradio] r6988 - usrp2/trunk/fpga/top/u2_sim

[matt]

Author: matt
Date: 2007-11-18 00:33:52 -0700 (Sun, 18 Nov 2007)
New Revision: 6988

Modified:
   usrp2/trunk/fpga/top/u2_sim/u2_sim_top.v
Log:
fixed some used-before-declared signals, connected tristate I2C signals for 
eeprom


Modified: usrp2/trunk/fpga/top/u2_sim/u2_sim_top.v
===================================================================
--- usrp2/trunk/fpga/top/u2_sim/u2_sim_top.v    2007-11-18 07:32:42 UTC (rev 
6987)
+++ usrp2/trunk/fpga/top/u2_sim/u2_sim_top.v    2007-11-18 07:33:52 UTC (rev 
6988)
@@ -126,7 +126,7 @@
    initial clk_to_mac = 0;
    always #4 clk_to_mac = ~clk_to_mac;
    
-   wire        div_clk;
+   wire        div_clk, dsp_clk;
    reg [7:0]   div_ctr = 0;
    
    assign      dsp_clk = clock_ready ? clk_fpga : aux_clk;
@@ -174,7 +174,7 @@
       .even(0),.error(0) );
    
    adc_model adc_model
-     (.clk(dsp_clk),
+     (.clk(dsp_clk),.rst(0),
       
.adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_oen_a(adc_oen_a),.adc_pdn_a(adc_pdn_a),
       
.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_oen_b(adc_oen_b),.adc_pdn_b(adc_pdn_b));
 
@@ -193,11 +193,35 @@
    
    xlnx_glbl glbl (.GSR(),.GTS());
    
-   M24LC024B eeprom(.A0(0),.A1(0),.A2(0),.WP(0),
-                   .SDA(SDA),.SCL(SCL),.RESET(0));
+   M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0),
+                         .SDA(SDA),.SCL(SCL),.RESET(0));
+
+   wire       scl_pad_i, scl_pad_o, scl_pad_oen_o;
+   wire       sda_pad_i, sda_pad_o, sda_pad_oen_o;
+   
    pullup p1(SCL);
    pullup p2(SDA);
+
+   assign     scl_pad_i = SCL;
+   assign     sda_pad_i = SDA;
+
+   assign     SCL = scl_pad_oen_o ? 1'bz : scl_pad_o;
+   assign     SDA = sda_pad_oen_o ? 1'bz : sda_pad_o;
+
+   // printf output
+   wire       uart_baud_o, uart_tx_o, uart_rx_i;
+   assign     uart_rx_i = 1'b1;
    
+   uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o));
+   
+   // End the simulation
+   always @(posedge wb_clk)
+     if((u2_basic.m0_we == 1'd1)&&(u2_basic.m0_adr == 16'hC2F0))
+       begin
+         $display($time, "Finish called.",);
+         $finish;
+       end
+   
    u2_basic u2_basic(.dsp_clk          (dsp_clk),
                     .wb_clk            (wb_clk),
                     .clock_ready       (clock_ready),
@@ -283,25 +307,4 @@
                     .clock_divider     (clock_divider)
                     );
 
-   // Experimental printf-like function
-   uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o));
-   
-   /*
-   reg               print_edge_det;
-   always @(posedge wb_clk)
-     begin
-       print_edge_det <= io_tx[7];
-       if(!print_edge_det & (io_tx[7] == 1'd1))
-         $write("%c",io_tx[15:8]);
-     end
-    */
-   
-   // End the simulation
-   always @(posedge wb_clk)
-     if((u2_basic.m0_we == 1'd1)&&(u2_basic.m0_adr == 16'hC2F0))
-       begin
-         $display($time, "Finish called.",);
-         $finish;
-       end
-   
 endmodule // u2_sim_top