[Commit-gnuradio] r6986 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2007-11-18 00:31:58 -0700 (Sun, 18 Nov 2007)
New Revision: 6986

Added:
   usrp2/trunk/fpga/control_lib/cascadefifo2.v
Modified:
   usrp2/trunk/fpga/control_lib/cascadefifo.v
Log:
fixed cascaded fifo and added a double cascased fifo


Modified: usrp2/trunk/fpga/control_lib/cascadefifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/cascadefifo.v  2007-11-18 07:31:20 UTC (rev 
6985)
+++ usrp2/trunk/fpga/control_lib/cascadefifo.v  2007-11-18 07:31:58 UTC (rev 
6986)
@@ -20,16 +20,16 @@
      output empty);
 
    wire [WIDTH-1:0] data_int;
-   wire            empty_int, full_int, transfer_int;
+   wire            empty_int, full_int, transfer;
    
    shortfifo #(.WIDTH(WIDTH)) shortfifo
      (.clk(clk),.rst(rst),
       .datain(datain), .write(write), .full(full),
-      .dataout(data_int), .read(transfer_int), .empty(empty_int) );
+      .dataout(data_int), .read(transfer), .empty(empty_int) );
 
    longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
      (.clk(clk),.rst(rst),
-      .datain(data_int), .write(transfer_int), .full(full_int),
+      .datain(data_int), .write(transfer), .full(full_int),
       .dataout(dataout), .read(read), .empty(empty) );
 
    assign          transfer = ~empty_int & ~full_int;      

Added: usrp2/trunk/fpga/control_lib/cascadefifo2.v
===================================================================
--- usrp2/trunk/fpga/control_lib/cascadefifo2.v                         (rev 0)
+++ usrp2/trunk/fpga/control_lib/cascadefifo2.v 2007-11-18 07:31:58 UTC (rev 
6986)
@@ -0,0 +1,45 @@
+
+
+// This FIFO exists to provide an intermediate point for the data on its
+// long trek from one RAM (in the buffer pool) to another (in the longfifo)
+// The shortfifo is more flexible in its placement since it is based on
+// distributed RAM
+
+// This one has the shortfifo on both the in and out sides.
+module cascadefifo2
+  #(parameter WIDTH=32, SIZE=9)
+    (input clk, input rst,
+     input [WIDTH-1:0] datain,
+     output [WIDTH-1:0] dataout,
+     input read,
+     input write,
+     output full,
+     output empty);
+
+   wire [WIDTH-1:0] data_int, data_int2;
+   wire            empty_int, full_int, transfer;
+   wire            empty_int2, full_int2, transfer2;
+   
+   shortfifo #(.WIDTH(WIDTH)) shortfifo
+     (.clk(clk),.rst(rst),
+      .datain(datain), .write(write), .full(full),
+      .dataout(data_int), .read(transfer), .empty(empty_int) );
+
+   longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
+     (.clk(clk),.rst(rst),
+      .datain(data_int), .write(transfer), .full(full_int),
+      .dataout(data_int2), .read(transfer2), .empty(empty_int2) );
+
+   shortfifo #(.WIDTH(WIDTH)) shortfifo2
+     (.clk(clk),.rst(rst),
+      .datain(data_int2), .write(transfer2), .full(full_int2),
+      .dataout(dataout), .read(read), .empty(empty) );
+
+   assign          transfer = ~empty_int & ~full_int;      
+   assign          transfer2 = ~empty_int2 & ~full_int2;           
+
+endmodule // cascadefifo2
+
+
+
+