[Commit-gnuradio] r6984 - usrp2/trunk/fpga/models

[matt]

Author: matt
Date: 2007-11-18 00:28:54 -0700 (Sun, 18 Nov 2007)
New Revision: 6984

Modified:
   usrp2/trunk/fpga/models/M24LC024B.v
Log:
end the write cycle in a reasonable time for sim purposes


Modified: usrp2/trunk/fpga/models/M24LC024B.v
===================================================================
--- usrp2/trunk/fpga/models/M24LC024B.v 2007-11-18 07:28:03 UTC (rev 6983)
+++ usrp2/trunk/fpga/models/M24LC024B.v 2007-11-18 07:28:54 UTC (rev 6984)
@@ -130,7 +130,8 @@
 // 
*******************************************************************************************************
 
    initial tAA = 900;                                  // SCL to SDA output 
delay
-   initial tWC = 5000000;                              // memory write cycle 
time
+   //initial tWC = 5000000;                            // memory write cycle 
time
+   initial tWC = 50000;                                // memory write cycle 
time
 
    initial begin
       SDA_DO = 0;