[Commit-gnuradio] r6981 - usrp2/trunk/fpga/top/u2_basic

[matt]

Author: matt
Date: 2007-11-17 17:55:45 -0700 (Sat, 17 Nov 2007)
New Revision: 6981

Modified:
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
cleanup debug pins


Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-11-17 23:51:36 UTC (rev 
6980)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-11-18 00:55:45 UTC (rev 
6981)
@@ -130,12 +130,11 @@
    wire        ram_loader_done;
    wire        ram_loader_rst, wb_rst, dsp_rst;
 
-   wire [31:0]         ser_debug;
-
    wire [31:0]         status, status_b0, status_b1, status_b2, status_b3, 
status_b4, status_b5, status_b6, status_b7;
    wire        bus_error, spi_int, i2c_int, timer_int, buffer_int, proc_int, 
overrun, underrun, uart_int;
 
-   wire [31:0]         debug_wb, debug_txmacfifo_in, debug_txmacfifo_out;
+   wire [31:0]         debug_gpio_0, debug_gpio_1;
+   wire [31:0]         debug_wb, debug_txmacfifo_in, debug_txmacfifo_out, 
debug_bufpool, debug_bufpool2;
    wire [15:0]         debug_gmii_1, debug_gmii_2;
 
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
@@ -225,7 +224,7 @@
                 .ram_loader_done_o(ram_loader_done));
 
    // Processor
-   aeMB_core_BE #(.ISIZ(16),.DSIZ(16))
+   aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(0))
      aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
           // Instruction Wishbone bus to I-RAM
           .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
@@ -331,7 +330,7 @@
    nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
                 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
                 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
-                .debug_0( debug_txmacfifo_in 
),.debug_1({debug_gmii_2,debug_gmii_1}),
+                .debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
                 .gpio( {io_tx,io_rx} ) );
    assign       s4_err = 1'b0;
    assign       s4_rty = 1'b0;
@@ -540,7 +539,6 @@
   
    // 
/////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
-
    
    wire [31:0] debug_cpld = 
{{ram_loader_we,ram_loader_done,clock_ready,ram_loader_ack,ram_loader_stb,ram_loader_rst,wb_rst,dsp_rst},
                             {ram_loader_done ? {2'b00, iwb_adr[13:0]} : 
{2'b00,ram_loader_adr[13:0]}},
@@ -553,22 +551,33 @@
    wire [31:0] debug_iram_dat = ram_loader_done ? iwb_dat : ram_loader_dat;
    
    assign      debug_wb = {m0_adr[15:0], m0_sel[3:0], m0_ack, m0_we, m0_stb, 
m0_err};
-
+   
    reg [13:0]  debug_gmii_1_reg, debug_gmii_2_reg;
+   
    always @(posedge GMII_GTX_CLK)
      debug_gmii_1_reg <=  
{GMII_COL,GMII_CRS,GMII_RX_DV,GMII_RX_ER,GMII_TX_EN,GMII_TX_ER,GMII_TXD[7:0]};
    always @(posedge GMII_RX_CLK)
      debug_gmii_2_reg <= 
{GMII_COL,GMII_CRS,GMII_RX_DV,GMII_RX_ER,GMII_TX_EN,GMII_TX_ER,GMII_RXD[7:0]};
-
+   
    assign      debug_gmii_1 = {GMII_GTX_CLK,GMII_TX_CLK,debug_gmii_1_reg};
    assign      debug_gmii_2 = {GMII_RX_CLK,1'b0,debug_gmii_2_reg};
-
+   
    assign      debug_txmacfifo_out = {Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, 
Tx_mac_eop, 1'b0, Tx_mac_data[26:0]};
    assign      debug_txmacfifo_in = {rd2_read, rd2_done, rd2_sop, rd2_eop, 
rd2_error, rd2_dat[26:0]};
-
-   assign      debug = debug_txmacfifo_out;
    
+   assign      debug_bufpool = {uart_baud_o,uart_tx_o,  GMII_TX_EN,GMII_TX_ER,
+                               PHY_INTn,buffer_int,timer_int,proc_int,
+                               GMII_TXD[7:0], status[15:0]  };
+   
+   assign      debug_bufpool2 = { led1,led2,iwb_adr[13:0],
+                                 Tx_mac_wa, Tx_mac_wr,rd2_read,rd2_done,
+                                 rd2_error,rd2_sop,rd2_eop,status_b0[8:0]  };
+   
+   assign      debug = 32'd0;
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
+
+   assign      debug_gpio_0 = 32'd0;
+   assign      debug_gpio_1 = 32'd0;
    
 endmodule // u2_basic