[Commit-gnuradio] r6978 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2007-11-17 16:14:34 -0700 (Sat, 17 Nov 2007)
New Revision: 6978

Added:
   usrp2/trunk/fpga/sdr_lib/round.v
Modified:
   usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v
Log:
rounding, plus include multipliers in rx chain


Modified: usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v      2007-11-17 22:33:41 UTC (rev 
6977)
+++ usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v      2007-11-17 23:14:34 UTC (rev 
6978)
@@ -19,8 +19,6 @@
    wire [23:0] i_decim, q_decim;
    wire [7:0]  decim_rate;
    
-   assign      sample = {i_decim[23:8],q_decim[23:8]};
-
    setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
@@ -43,10 +41,30 @@
    
    strobe_gen 
strobe_gen(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate),
                         .strobe_in(1),.strobe(strobe) );
+
+   wire [35:0] prod_i, prod_q;
    
+   MULT18X18S mult_i
+     (.P(prod_i),    // 36-bit multiplier output
+      .A({{4{adc_a[13]}},adc_a} ),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+
+   MULT18X18S mult_q
+     (.P(prod_q),    // 36-bit multiplier output
+      .A({{4{adc_b[13]}},adc_b} ),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      ); 
+
    cordic #(.bitwidth(24))
      cordic(.clock(clk), .reset(rst), .enable(run),
-           .xi({adc_a,10'b0}),. yi({adc_b,10'b0}), .zi(phase[31:16]),
+           .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:16]),
            .xo(i_bb),.yo(q_bb),.zo() );
 
    cic_decim #(.bw(24))
@@ -58,5 +76,11 @@
      decim_q (.clock(clk),.reset(rst),.enable(run),
              .rate(decim_rate),.strobe_in(1'b1),.strobe_out(strobe),
              .signal_in(q_bb),.signal_out(q_decim));
-   
+
+   wire [15:0] i_out, q_out;
+   round #(.bits_in(24),.bits_out(16)) round_i (.in(i_decim),.out(i_out));
+   round #(.bits_in(24),.bits_out(16)) round_q (.in(q_decim),.out(q_out));
+
+   assign      sample = {i_out,q_out};
+
 endmodule // dsp_core_rx

Added: usrp2/trunk/fpga/sdr_lib/round.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/round.v                            (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/round.v    2007-11-17 23:14:34 UTC (rev 6978)
@@ -0,0 +1,33 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2007 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Rounding "macro"
+// Keeps the topmost bits, does proper 2s comp rounding
+
+module round
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input [bits_in-1:0] in,
+     output [bits_out-1:0] out);
+   
+   assign out = in[bits_in-1:bits_in-bits_out] + in[bits_in-1] & 
|in[bits_in-bits_out-1:0];
+   
+endmodule // round