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[Commit-gnuradio] r6970 - in gnuradio/branches/developers/zhuochen/inban
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From: |
zhuochen |
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Subject: |
[Commit-gnuradio] r6970 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib toplevel/usrp_inband_usb |
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Date: |
Fri, 16 Nov 2007 14:32:49 -0700 (MST) |
Author: zhuochen
Date: 2007-11-16 14:32:48 -0700 (Fri, 16 Nov 2007)
New Revision: 6970
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
We fix the performance problem. We used max payload size for all incoming data
packets to minimize overhead to data ratio.
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
2007-11-16 20:06:42 UTC (rev 6969)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
2007-11-16 21:32:48 UTC (rev 6970)
@@ -1,152 +1,148 @@
-module packet_builder #(parameter NUM_CHAN = 1)(
- // System
- input rxclk,
- input reset,
- input [31:0] adctime,
- input [3:0] channels,
- // ADC side
- input [15:0]chan_fifodata,
- input [NUM_CHAN:0]chan_empty,
- input [9:0]chan_usedw,
- output reg [3:0]rd_select,
- output reg chan_rdreq,
- // FX2 side
- output reg WR,
- output reg [15:0]fifodata,
- input have_space,
- input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire
[31:0]rssi_2,
- input wire [31:0]rssi_3, output wire [7:0] debugbus,
- input [NUM_CHAN:0] underrun);
-
-
- // States
- `define IDLE 3'd0
- `define HEADER1 3'd1
- `define HEADER2 3'd2
- `define TIMESTAMP 3'd3
- `define FORWARD 3'd4
-
- `define MAXPAYLOAD 504
-
- `define PAYLOAD_LEN 8:0
- `define TAG 12:9
- `define MBZ 15:13
-
- `define CHAN 4:0
- `define RSSI 10:5
- `define BURST 12:11
- `define DROPPED 13
- `define UNDERRUN 14
- `define OVERRUN 15
-
- reg [NUM_CHAN:0] overrun;
- reg [2:0] state;
- reg [8:0] read_length;
- reg [8:0] payload_len;
- reg tstamp_complete;
- reg [3:0] check_next;
- wire [8:0] chan_used;
- wire [31:0] true_rssi;
- wire [4:0] true_channel;
- wire ready_to_send;
+module packet_builder #(parameter NUM_CHAN = 1)
+( //System
+ input rxclk, input reset, input [31:0]adctime,
+ //ADC side
+ input [15:0]chan_fifodata, input [9:0]chan_usedw,
+ output reg[3:0]rd_select, output reg chan_rdreq,
+ //FX2 side
+ output reg WR, output reg [15:0]fifodata, input have_space,
+ //misc
+ input wire [5:0] rssi, output wire [7:0] debugbus,
+ input chan_underrun, input rx_WR_done, output reg rx_WR_enabled);
- assign debugbus = {state, chan_empty[0], underrun[0], check_next[0],
- have_space, rd_select[0]};
- assign chan_used = chan_usedw[8:0];
- assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
- ((rd_select[0]) ?
rssi_1:rssi_0);
- assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next -
4'd1});
- assign ready_to_send = (chan_used == 9'd504) ||
- ((rd_select == NUM_CHAN)&&(chan_used > 0));
-
- always @(posedge rxclk)
- begin
- if (reset)
- begin
- overrun <= 0;
- WR <= 0;
- rd_select <= 0;
- chan_rdreq <= 0;
- tstamp_complete <= 0;
- check_next <= 0;
- state <= `IDLE;
- end
- else case (state)
- `IDLE: begin
- chan_rdreq <= #1 0;
- //check if the channel is full
- if(~chan_empty[check_next])
- begin
- if (have_space)
- begin
- //transmit if the usb buffer
have space
- //check if we should send
- if (ready_to_send)
- state <= #1 `HEADER1;
-
- overrun[check_next] <= 0;
- end
- else
- begin
- //wait if the usb buffer is
full and set overrun
- state <= #1 `IDLE;
- overrun[check_next] <= 1;
- end
- rd_select <= #1 check_next;
- end
- check_next <= #1 (check_next == channels ? 4'd0
: check_next + 4'd1);
+
+ //states
+
+ `define IDLE 3'd0
+ `define HEADER1 3'd1
+ `define HEADER2 3'd2
+ `define TIMESTAMP1 3'd3
+ `define TIMESTAMP2 3'd4
+ `define FORWARD 3'd5
+
+ //variables
+ `define STDPAYLOAD 9'd504
+
+ //packet fields
+ `define PAYLOAD_LEN 8:0
+ `define TAG 12:9
+ `define MBZ 15:13
+ `define CHAN 4:0
+ `define RSSI 10:5
+ `define BURST 12:11
+ `define DROPPED 13
+ `define UNDERRUN 14
+ `define OVERRUN 15
+
+ //registers
+ reg [2:0] state;
+ reg [8:0] payload_len;
+ reg [8:0] payload_read;
+ reg [NUM_CHAN:0]overrun;
+
+ //wires
+ wire channel_ready;
+ //command packet is ready if command packet is ready to be sent or data
+ //packet contain enough data
+ assign channel_ready = (rd_select == NUM_CHAN) ? (chan_usedw > 0 &&
rx_WR_done) :
+ (chan_usedw >= `STDPAYLOAD);
+ wire [8:0] channel_payload;
+ //payload of data packets are always 504 and the payload of command packets
+ //varies
+ assign channel_payload = (rd_select == NUM_CHAN) ? (chan_usedw[8:0]) :
`STDPAYLOAD;
+ wire [4:0] channel_name;
+ //channel name is the index of the channel except for command channel where
+ //index is 5'h1f
+ assign channel_name = (rd_select == NUM_CHAN) ? (5'h1f) : (rd_select);
+
+ assign debugbus = {1'd0, rxclk, state, rd_select[0], have_space,
channel_ready};
+ always @(posedge rxclk)
+ begin
+ if (reset)
+ begin
+ state <= 0;
+ payload_read <= 0;
+ overrun <= 0;
+ rd_select <= 0;
+ WR <= 0;
+ rx_WR_enabled <= 1;
+ end
+ else case (state)
+ `IDLE:
+ begin
+ chan_rdreq <= 0;
+ //check if a packet is ready to be sent
+ if (have_space & channel_ready)
+ begin
+ state <= `HEADER1;
+ if (rd_select == NUM_CHAN)
+ begin
+ rx_WR_enabled <= 0;
+ end
+ end
+ if (~have_space & channel_ready)
+ begin
+ overrun[rd_select] <= 1;
+ end
+ if (have_space & ~channel_ready)
+ begin
+ rd_select <= (rd_select == NUM_CHAN) ? 0: (rd_select +
4'd1);
+ end
+ end
+ `HEADER1:
+ begin
+ fifodata[`PAYLOAD_LEN] <= channel_payload;
+ fifodata[`TAG] <= 0;
+ fifodata[`MBZ] <= 0;
+ payload_len <= channel_payload;
+ payload_read <= 0;
+ WR <= 1;
+ state <= `HEADER2;
+ end
+ `HEADER2:
+ begin
+ fifodata[`CHAN] <= channel_name;
+ fifodata[`RSSI] <= rssi;
+ fifodata[`BURST] <= 0;
+ fifodata[`DROPPED] <= 0;
+ fifodata[`UNDERRUN] <= chan_underrun;
+ fifodata[`OVERRUN] <= overrun[rd_select];
+ state <= `TIMESTAMP1;
end
-
- `HEADER1: begin
- fifodata[`PAYLOAD_LEN] <= #1 9'd504;
- payload_len <= #1 9'd504;
- fifodata[`TAG] <= #1 0;
- fifodata[`MBZ] <= #1 0;
- WR <= #1 1;
-
- state <= #1 `HEADER2;
- read_length <= #1 0;
+
+ `TIMESTAMP1:
+ begin
+ fifodata <= adctime[15:0];
+ state <= `TIMESTAMP2;
end
-
- `HEADER2: begin
- fifodata[`CHAN] <= #1 true_channel;
- fifodata[`RSSI] <= #1 true_rssi[5:0];
- fifodata[`BURST] <= #1 0;
- fifodata[`DROPPED] <= #1 0;
- fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 :
underrun[true_channel];
- fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 :
overrun[true_channel];
- state <= #1 `TIMESTAMP;
+ `TIMESTAMP2:
+ begin
+ fifodata <= adctime[31:16];
+ state <= `FORWARD;
+ chan_rdreq <= 1;
end
-
- `TIMESTAMP: begin
- fifodata <= #1 (tstamp_complete ? adctime[31:16] :
adctime[15:0]);
- tstamp_complete <= #1 ~tstamp_complete;
-
- if (~tstamp_complete)
- chan_rdreq <= #1 1;
-
- state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
+ `FORWARD:
+ begin
+ if (payload_read >= `STDPAYLOAD)
+ begin
+ WR <= 0;
+ state <= `IDLE;
+ rx_WR_enabled <= 1;
+ end
+ else
+ begin
+ if (payload_len == payload_read + 9'd2)
+ begin
+ chan_rdreq <= 0;
+ end
+ payload_read <= payload_read + 9'd2;
+ fifodata <= chan_fifodata;
+ end
end
-
- `FORWARD: begin
- read_length <= #1 read_length + 9'd2;
- fifodata <= #1 (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
-
- if (read_length >= `MAXPAYLOAD)
- begin
- WR <= #1 0;
- state <= #1 `IDLE;
- chan_rdreq <= #1 0;
- end
- else if (read_length == payload_len - 4)
- chan_rdreq <= #1 0;
+ default:
+ begin
+ state <= `IDLE;
end
-
- default: begin
- //handling error state
- state <= `IDLE;
- end
- endcase
+ endcase
end
endmodule
-
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-11-16 20:06:42 UTC (rev 6969)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-11-16 21:32:48 UTC (rev 6970)
@@ -104,7 +104,7 @@
assign rssi_wait = out[2];
assign strobe_wr = strobe;
- always @(*)
+ always @(posedge clk)
if (reset | ~enable[1])
begin
strobe <= 0;
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-11-16 20:06:42 UTC (rev 6969)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-11-16 21:32:48 UTC (rev 6970)
@@ -1,179 +1,120 @@
-//`include "../../firmware/include/fpga_regs_common.v"
-//`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer_inband
- ( input usbclk,
- input bus_reset,
- input reset, // DSP side reset (used here), do not reset registers
- input reset_regs, //Only reset registers
- output [15:0] usbdata,
- input RD,
- output wire have_pkt_rdy,
- output reg rx_overrun,
- input wire [3:0] channels,
- input wire [15:0] ch_0,
- input wire [15:0] ch_1,
- input wire [15:0] ch_2,
- input wire [15:0] ch_3,
- input wire [15:0] ch_4,
- input wire [15:0] ch_5,
- input wire [15:0] ch_6,
- input wire [15:0] ch_7,
- input rxclk,
- input rxstrobe,
- input clear_status,
- input [6:0] serial_addr,
- input [31:0] serial_data,
- input serial_strobe,
- output wire [15:0] debugbus,
-
- //Connection with tx_inband
- input rx_WR,
- input [15:0] rx_databus,
- input rx_WR_done,
- output reg rx_WR_enabled,
- //signal strength
- input wire [31:0] rssi_0, input wire [31:0] rssi_1,
- input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- input wire [1:0] tx_underrun
- );
+ ( input usbclk, input bus_reset, input reset, input reset_regs,
+ output [15:0] usbdata, input RD, output wire have_pkt_rdy,
+ output reg rx_overrun, input wire [3:0] channels,
+ input wire [15:0] ch_0, input wire [15:0] ch_1, input wire [15:0] ch_2,
+ input wire [15:0] ch_3, input wire [15:0] ch_4, input wire [15:0] ch_5,
+ input wire [15:0] ch_6, input wire [15:0] ch_7, input rxclk, input
rxstrobe,
+ input clear_status, output wire [15:0] debugbus,
+ input rx_WR, input [15:0] rx_databus, input rx_WR_done, output wire
rx_WR_enabled,
+ input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+ input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+ input wire [1:0] tx_underrun);
+
+ parameter NUM_CHAN = 1;
+ genvar i ;
+ wire [3:0] rd_select;
- parameter NUM_CHAN = 1;
- genvar i ;
-
- // FX2 Bug Fix
- reg [8:0] read_count;
- always @(negedge usbclk)
- if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
- else
- read_count <= #1 RD ? read_count : 9'b0;
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
- // Time counter
- reg [31:0] adctime;
- always @(posedge rxclk)
- if (reset)
- adctime <= 0;
- else if (rxstrobe)
- adctime <= adctime + 1;
-
- // USB side fifo
- wire [11:0] rdusedw;
- wire [11:0] wrusedw;
- wire [15:0] fifodata;
- wire WR;
- wire have_space;
+ // Time counter
+ reg [31:0] adctime;
+ always @(posedge rxclk)
+ if (reset)
+ adctime <= 0;
+ else if (rxstrobe)
+ adctime <= adctime + 1;
- fifo_4kx16_dc rx_usb_fifo (
- .aclr ( reset ),
- .data ( fifodata ),
- .rdclk ( ~usbclk ),
- .rdreq ( RD & ~read_count[8] ),
- .wrclk ( rxclk ),
- .wrreq ( WR ),
- .q ( usbdata ),
- .rdempty ( ),
- .rdusedw ( rdusedw ),
- .wrfull ( ),
- .wrusedw ( wrusedw ) );
-
- assign have_pkt_rdy = (rdusedw >= 12'd256);
- assign have_space = (wrusedw < 12'd760);
-
- // Rx side fifos
- wire chan_rdreq;
- wire [15:0] chan_fifodata;
- wire [9:0] chan_usedw;
- wire [NUM_CHAN:0] chan_empty;
- wire [3:0] rd_select;
- wire [NUM_CHAN:0] rx_full;
-
- packet_builder #(NUM_CHAN) rx_pkt_builer (
- .rxclk ( rxclk ),
- .reset ( reset ),
- .adctime ( adctime ),
- .channels ( 4'd1 ), //need to be tested and changed to channels
- .chan_rdreq ( chan_rdreq ),
- .chan_fifodata ( chan_fifodata ),
- .chan_empty ( chan_empty ),
- .rd_select ( rd_select ),
- .chan_usedw ( chan_usedw ),
- .WR ( WR ),
- .fifodata ( fifodata ),
- .have_space ( have_space ),
- .rssi_0(rssi_0), .rssi_1(rssi_1),
- .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
- .underrun(tx_underrun));
-
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(rx_full[0])
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
+ //usb side fifo
+ wire [11:0] wrusedw;
+ wire [11:0] rdusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
- reg [6:0] test;
- always @(posedge rxclk)
- if (reset)
- test <= 0;
- else
- test <= test + 7'd1;
-
- // TODO write this genericly
- wire [15:0]ch[NUM_CHAN:0];
- assign ch[0] = ch_0;
-
- wire cmd_empty;
- always @(posedge rxclk)
- if(reset)
- rx_WR_enabled <= 1;
- else if(cmd_empty)
- rx_WR_enabled <= 1;
- else if(rx_WR_done)
- rx_WR_enabled <= 0;
+ fifo_4kx16_dc rx_usb_fifo
+ (.aclr(reset), .data(fifodata), .rdclk(~usbclk), .rdreq(RD & ~read_count[8]),
+ .wrclk(rxclk), .wrreq(WR), .q(usbdata), .wrusedw(wrusedw),
.rdusedw(rdusedw));
- wire [15:0] dataout [0:NUM_CHAN];
- wire [9:0] usedw [0:NUM_CHAN];
- wire empty[0:NUM_CHAN];
-
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
- begin : generate_channel_fifos
- wire rdreq;
+ assign have_space = (wrusedw < 12'd760);
+ assign have_pkt_rdy = (rdusedw >= 12'd512);
- assign rdreq = (rd_select == i) & chan_rdreq;
+ //need to change the parameters later to make this more robust
+ wire [31:0] rssi;
+ assign rssi = rd_select[0] ? rssi_1: rssi_0;
+ wire chan_underrun;
+ assign chan_underrun = rd_select[0] ? tx_underrun[1] : tx_underrun[0];
- fifo_1kx16 rx_chan_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( ch[i] ),
- .rdreq ( rdreq ),
- .wrreq ( ~rx_full[i] & rxstrobe),
- .empty (empty[i]),
- .full (rx_full[i]),
- .q ( dataout[i]),
- .usedw ( usedw[i]),
- .almost_empty(chan_empty[i])
- );
- end
- endgenerate
- wire [7:0] debug;
- fifo_1kx16 rx_cmd_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( rx_databus ),
- .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
- .wrreq ( rx_WR & rx_WR_enabled),
- .empty ( cmd_empty),
- .full ( rx_full[NUM_CHAN] ),
- .q ( dataout[NUM_CHAN]),
- .usedw ( usedw[NUM_CHAN] )
- );
- assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
- assign chan_fifodata = dataout[rd_select];
- assign chan_usedw = usedw[rd_select];
- assign debugbus = {rxstrobe, chan_rdreq, debug,
- rx_full[0], chan_empty[0], empty[0],
have_space, RD, rxclk};
+ wire [7:0] pb_debug;
+ wire [31:0] chan_fifodata;
+ wire [9:0] chan_usedw;
+ wire chan_rdreq;
+
+ packet_builder #(NUM_CHAN) rx_pkt_builder
+ (.rxclk(rxclk), .reset(reset), .adctime(adctime),
+ .chan_fifodata(chan_fifodata), .chan_usedw(chan_usedw),
+ .rd_select(rd_select), .chan_rdreq(chan_rdreq), .WR(WR),
+ .fifodata(fifodata), .have_space(have_space),
+ .rssi(rssi[5:0]), .debugbus(pb_debug), .chan_underrun(chan_underrun),
+ .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled));
+
+ // Detect overrun
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(usedw[0]>=10'd1008)
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
+
+ wire [15:0]ch[7:0];
+ assign ch[0] = ch_0;
+ assign ch[1] = ch_1;
+ assign ch[2] = ch_2;
+ assign ch[3] = ch_3;
+ assign ch[4] = ch_4;
+ assign ch[5] = ch_5;
+ assign ch[6] = ch_6;
+ assign ch[7] = ch_7;
+
+ wire [15:0] dataout [0:NUM_CHAN];
+ wire [9:0] usedw [0:NUM_CHAN];
+
+ generate for (i = 0; i < NUM_CHAN; i = i + 1)
+ begin : generate_channel_fifos
+ wire rdreq;
+
+ assign rdreq = (rd_select == i) & chan_rdreq;
+
+ fifo_1kx16 rx_chan_fifo
+ (.aclr(reset), .clock(rxclk), .data(ch[i]), .rdreq(rdreq),
+ .wrreq((usedw[i]<=10'd1008) & rxstrobe), .q(dataout[i]),
+ .usedw(usedw[i]));
+
+ end
+ endgenerate
+
+ fifo_1kx16 rx_cmd_fifo
+ (.aclr(reset), .clock(rxclk), .data(rx_databus),
+ .rdreq((rd_select == NUM_CHAN) & chan_rdreq),
+ .wrreq(rx_WR & rx_WR_enabled), .q(dataout[NUM_CHAN]),
+ .usedw(usedw[NUM_CHAN]));
+
+ assign chan_fifodata = dataout[rd_select];
+ assign chan_usedw = usedw[rd_select];
+ wire [9:0] tmp;
+ assign tmp = usedw[0];
+ assign debugbus = {usbclk, rxclk, tmp[9:2], have_space, have_pkt_rdy,
+ (usedw[0]<=10'd1008) , rxstrobe, chan_rdreq,
rd_select[0]};
+
endmodule
+
+
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-11-16 20:06:42 UTC (rev 6969)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-11-16 21:32:48 UTC (rev 6970)
@@ -263,12 +263,11 @@
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
-
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
- .debugbus(),
+ .debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`else
@@ -448,7 +447,6 @@
// Misc Settings
setting_reg #(`FR_MODE)
sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
reg forb;
- assign tx_debugbus = {4'd0, forb, serial_addr, strobe_db, strobe_wr, clk64,
usbclk};
always @(posedge usbclk)
begin
if (strobe_db) forb <= 1;
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- [Commit-gnuradio] r6970 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib toplevel/usrp_inband_usb,
zhuochen <=