[Commit-gnuradio] r6944 - in gnuradio/branches/developers/matt/u2f: control_lib opencores/aemb/rtl/verilog top/u2_basic top/u2_fpga

[matt]

Author: matt
Date: 2007-11-15 19:38:44 -0700 (Thu, 15 Nov 2007)
New Revision: 6944

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/ram_wb_harvard.v
   
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
Log:
switchover to the new processor and 2x divider instead of 3x


Modified: gnuradio/branches/developers/matt/u2f/control_lib/ram_wb_harvard.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/ram_wb_harvard.v  
2007-11-16 02:30:44 UTC (rev 6943)
+++ gnuradio/branches/developers/matt/u2f/control_lib/ram_wb_harvard.v  
2007-11-16 02:38:44 UTC (rev 6944)
@@ -32,7 +32,7 @@
    
    // Instruction Read Port
    always @(posedge wb_clk_i)
-     iwb_ack_o <= iwb_stb_i;
+     iwb_ack_o <= iwb_stb_i & ~iwb_ack_o;
    
    always @(posedge wb_clk_i)
      iwb_dat_o[31:24] <= ram3[iwb_adr_i[AWIDTH-1:2]];
@@ -58,7 +58,7 @@
    
    // Data Port
    always @(posedge wb_clk_i)
-     dwb_ack_o <= dwb_stb_i;
+     dwb_ack_o <= dwb_stb_i & ~dwb_ack_o;
    
    always @(posedge wb_clk_i)
      dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];

Modified: 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
===================================================================
--- 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v 
    2007-11-16 02:30:44 UTC (rev 6943)
+++ 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v 
    2007-11-16 02:38:44 UTC (rev 6944)
@@ -29,10 +29,10 @@
 
    assign  dwb_cyc_o = dwb_stb_o;
 
-//`define NEW_AEMB 1
+`define NEW_AEMB 1
 `ifdef NEW_AEMB
-   aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ))
-     aeMB_edk32 (.sys_clk_i(~sys_clk_i), 
+   aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(0),.BSF(0))
+     aeMB_edk32 (.sys_clk_i(sys_clk_i), 
                 .sys_rst_i(sys_rst_i),
                 
                 .iwb_stb_o(iwb_stb_o),

Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-11-16 02:30:44 UTC (rev 6943)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-11-16 02:38:44 UTC (rev 6944)
@@ -203,14 +203,12 @@
    
    // ///////////////////////////////////////////////////////////////////
    // RAM Loader
-   wire         iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, 
iram_wr_we;
-   wire [3:0]   iram_wr_sel;
-   wire [aw-1:0] iram_wr_adr, iram_rd_adr;
-   wire [dw-1:0] iram_wr_dat, iram_rd_dat;
 
-   assign       iram_rd_ack = ram_loader_done ? iram_ack : 1'b0;
-   assign       iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack;
-   
+   wire [31:0]          ram_loader_dat, iwb_dat;
+   wire [13:0]          ram_loader_adr, iwb_adr;
+   wire [3:0]   ram_loader_sel;
+   wire         ram_loader_stb, ram_loader_we, ram_loader_ack;
+   wire         iwb_ack, iwb_stb;
    ram_loader #(.AWIDTH(16))
      ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
                 // CPLD Interface
@@ -221,17 +219,17 @@
                 .done_o(cpld_done),
                 .detached_i(cpld_detached),
                 // Wishbone Interface
-                .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr),
-                .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel),
-                .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack),
+                .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
+                
.wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
+                .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
                 .ram_loader_done_o(ram_loader_done));
 
    // Processor
    aeMB_core_BE #(.ISIZ(16),.DSIZ(16))
      aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
           // Instruction Wishbone bus to I-RAM
-          .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr),
-          .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack),
+          .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
+          .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
           // Data Wishbone bus to system bus fabric
           
.dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
           
.dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
@@ -242,18 +240,21 @@
    
    // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
    // I-port connects directly to processor and ram loader
-   
-   ram_wb_harvard #(.AWIDTH(14))
-     ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+
+   ram_harv_cache #(.AWIDTH(14),.ICWIDTH(7),.DCWIDTH(6))
+     sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
             
-            .iwb_adr_i(ram_loader_done ? iram_rd_adr : 
iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat),
-            .iwb_we_i(ram_loader_done ? 1'b0 : 
iram_wr_we),.iwb_ack_o(iram_ack),
-            .iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb),
-            .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel),
+            .ram_loader_adr_i(ram_loader_adr), 
.ram_loader_dat_i(ram_loader_dat),
+            .ram_loader_stb_i(ram_loader_stb), 
.ram_loader_sel_i(ram_loader_sel),
+            .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+            .ram_loader_done_i(ram_loader_done),
             
-            .dwb_adr_i(s0_adr[13:0]),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i),
-            
.dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel));
-
+            .iwb_adr_i(iwb_adr), .iwb_stb_i(iwb_stb),
+            .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+            
+            .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), 
.dwb_dat_o(s0_dat_i),
+            .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), 
.dwb_sel_i(s0_sel));
+   
    assign       s0_err = 1'b0;
    assign       s0_rty = 1'b0;
 
@@ -541,15 +542,15 @@
    // Debug Pins
 
    
-   wire [31:0] debug_cpld = 
{{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst},
-                            {ram_loader_done ? {iram_rd_adr[15:0]} : 
iram_wr_adr[15:0]},
+   wire [31:0] debug_cpld = 
{{ram_loader_we,ram_loader_done,clock_ready,ram_loader_ack,ram_loader_stb,ram_loader_rst,wb_rst,dsp_rst},
+                            {ram_loader_done ? {2'b00, iwb_adr[13:0]} : 
{2'b00,ram_loader_adr[13:0]}},
                             
{proc_int,timer_int,cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached}
 };
    
-   wire [31:0] debug_new = {{ram_loader_done ? {iram_rd_adr[15:0]} : 
iram_wr_adr[15:0]},
+   wire [31:0] debug_new = {{ram_loader_done ? {2'b00, iwb_adr[13:0]} : 
{2'b00, ram_loader_adr[13:0]}},
                            {3'b0,ram_loader_done,clock_ready, wb_rst, 
proc_int,timer_int},
                            {1'b0, 
GMII_TX_CLK,clk_to_mac,PHY_CLK,MDC,MDIO,PHY_INTn,PHY_RESETn} };
    
-   wire [31:0] debug_iram_dat = ram_loader_done ? iram_rd_dat : iram_wr_dat;
+   wire [31:0] debug_iram_dat = ram_loader_done ? iwb_dat : ram_loader_dat;
    
    assign      debug_wb = {m0_adr[15:0], m0_sel[3:0], m0_ack, m0_we, m0_stb, 
m0_err};
 


Property changes on: gnuradio/branches/developers/matt/u2f/top/u2_fpga
___________________________________________________________________
Name: svn:ignore
   - templates
_ngo
_xmsgs
*.bit
*.bin
*.stx
*.par
*.unroutes
*.ntrc_log
*.ngr
*.mrp
*.html
*.lso
*.twr
*.bld
*.ncd
*.txt
*.cmd_log
*.drc
*.map
*.twr
*.xml
*.syr
*.ngm
*.xst
*.csv
*.html
*.lock
*.ncd
*.twx
*.ise_ISE_Backup
*.xml
*.ut
*.xpi
*.ngd
*.ncd
*.pad
*.bgn
*.ngc
*.pcf
*.ngd
xst
*.log
*.rpt
*.cel
*.restore

   + templates
netgen
_ngo
_xmsgs
_pace.ucf
*.cmd
*.ibs
*.lfp
*.mfp
*.bit
*.bin
*.stx
*.par
*.unroutes
*.ntrc_log
*.ngr
*.mrp
*.html
*.lso
*.twr
*.bld
*.ncd
*.txt
*.cmd_log
*.drc
*.map
*.twr
*.xml
*.syr
*.ngm
*.xst
*.csv
*.html
*.lock
*.ncd
*.twx
*.ise_ISE_Backup
*.xml
*.ut
*.xpi
*.ngd
*.ncd
*.pad
*.bgn
*.ngc
*.pcf
*.ngd
xst
*.log
*.rpt
*.cel
*.restore


Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf       
2007-11-16 02:30:44 UTC (rev 6943)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf       
2007-11-16 02:38:44 UTC (rev 6944)
@@ -213,23 +213,6 @@
 NET "ser_t[7]"  LOC = "AA5"  ;
 NET "ser_t[8]"  LOC = "W6"  ;
 NET "ser_t[9]"  LOC = "V6"  ;
-NET "clk_muxed" TNM_NET = "clk_muxed";
-TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
-NET "clk_to_mac" TNM_NET = "clk_to_mac";
-TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
-NET "u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" TNM_NET = 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT";
-TIMESPEC "TS_u2_basic_MAC_top_U_Clk_ctrl_U_1_CLK_DIV2_OUT" = PERIOD 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" 16 ns HIGH 50 %;
-NET "cpld_clk" TNM_NET = "cpld_clk";
-TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
-NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
-TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
-NET "GMII_TX_CLK" TNM_NET = "GMII_TX_CLK";
-TIMESPEC "TS_GMII_TX_CLK" = PERIOD "GMII_TX_CLK" 8 ns HIGH 50 %;
-NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
-TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
-#PACE: Start of Constraints generated by PACE
-
-#PACE: Start of PACE I/O Pin Assignments
 NET "adc_oen_a"  LOC = "E19"  ; 
 NET "adc_oen_b"  LOC = "C17"  ; 
 NET "adc_ovf_a"  LOC = "F18"  ; 
@@ -315,8 +298,19 @@
 NET "ser_tkmsb"  LOC = "U11"  ; 
 NET "ser_tx_clk"  LOC = "U7"  ; 
 
-#PACE: Start of PACE Area Constraints
-
-#PACE: Start of PACE Prohibit Constraints
-
 #PACE: End of Constraints generated by PACE
+
+NET "clk_muxed" TNM_NET = "clk_muxed";
+TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+NET "u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" TNM_NET = 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT";
+TIMESPEC "TS_u2_basic_MAC_top_U_Clk_ctrl_U_1_CLK_DIV2_OUT" = PERIOD 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" 16 ns HIGH 50 %;
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+NET "GMII_TX_CLK" TNM_NET = "GMII_TX_CLK";
+TIMESPEC "TS_GMII_TX_CLK" = PERIOD "GMII_TX_CLK" 8 ns HIGH 50 %;
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj   
2007-11-16 02:30:44 UTC (rev 6943)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj   
2007-11-16 02:38:44 UTC (rev 6944)
@@ -1,14 +1,21 @@
+verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
 verilog work "../../eth/rtl/verilog/TECH/duram.v"
+verilog work "../../control_lib/ram_2port.v"
 verilog work "../../sdr_lib/sign_extend.v"
 verilog work "../../sdr_lib/cordic_stage.v"
 verilog work "../../sdr_lib/cic_int_shifter.v"
 verilog work "../../sdr_lib/cic_dec_shifter.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v"
 verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_regfile.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_fetch.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_decode.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_control.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_aslu.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
 verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
 verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
 verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
@@ -29,14 +36,18 @@
 verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
-verilog work "../../control_lib/ram_2port.v"
+verilog work "../../control_lib/shortfifo.v"
+verilog work "../../control_lib/longfifo.v"
 verilog work "../../sdr_lib/cordic.v"
 verilog work "../../sdr_lib/cic_interp.v"
 verilog work "../../sdr_lib/cic_decim.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v"
 verilog work "../../opencores/spi/rtl/verilog/spi_shift.v"
 verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
 verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
-verilog work "../../opencores/aemb/rtl/verilog/aeMB_core.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v"
 verilog work "../../eth/rtl/verilog/eth_miim.v"
 verilog work "../../eth/rtl/verilog/RMON.v"
 verilog work "../../eth/rtl/verilog/Phy_int.v"
@@ -45,18 +56,20 @@
 verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
 verilog work "../../control_lib/strobe_gen.v"
 verilog work "../../control_lib/ss_rcvr.v"
-verilog work "../../control_lib/shortfifo.v"
 verilog work "../../control_lib/setting_reg.v"
 verilog work "../../control_lib/mux8.v"
 verilog work "../../control_lib/mux4.v"
-verilog work "../../control_lib/longfifo.v"
+verilog work "../../control_lib/icache.v"
+verilog work "../../control_lib/dpram32.v"
 verilog work "../../control_lib/decoder_3_8.v"
+verilog work "../../control_lib/cascadefifo.v"
 verilog work "../../control_lib/buffer_int.v"
 verilog work "../../control_lib/CRC16_D16.v"
 verilog work "../../sdr_lib/tx_control.v"
 verilog work "../../sdr_lib/rx_control.v"
 verilog work "../../sdr_lib/dsp_core_tx.v"
 verilog work "../../sdr_lib/dsp_core_rx.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v"
 verilog work "../../opencores/spi/rtl/verilog/spi_top.v"
 verilog work "../../opencores/simple_pic/rtl/simple_pic.v"
 verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
@@ -71,8 +84,8 @@
 verilog work "../../control_lib/settings_bus.v"
 verilog work "../../control_lib/serdes_tx.v"
 verilog work "../../control_lib/serdes_rx.v"
-verilog work "../../control_lib/ram_wb_harvard.v"
 verilog work "../../control_lib/ram_loader.v"
+verilog work "../../control_lib/ram_harv_cache.v"
 verilog work "../../control_lib/nsgpio.v"
 verilog work "../../control_lib/buffer_pool.v"
 verilog work "../u2_basic/u2_basic.v"

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v     
2007-11-16 02:30:44 UTC (rev 6943)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v     
2007-11-16 02:38:44 UTC (rev 6944)
@@ -193,7 +193,7 @@
                  .PSDONE(), 
                  .STATUS());
    defparam DCM_INST.CLK_FEEDBACK = "1X";
-   defparam DCM_INST.CLKDV_DIVIDE = 3.0;
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
    defparam DCM_INST.CLKFX_DIVIDE = 1;
    defparam DCM_INST.CLKFX_MULTIPLY = 4;
    defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";