[Commit-gnuradio] r6941 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-11-15 18:51:10 -0700 (Thu, 15 Nov 2007)
New Revision: 6941

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/dpram32.v
Log:
xilinx likes this rewording better


Modified: gnuradio/branches/developers/matt/u2f/control_lib/dpram32.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/dpram32.v 2007-11-16 
00:42:11 UTC (rev 6940)
+++ gnuradio/branches/developers/matt/u2f/control_lib/dpram32.v 2007-11-16 
01:51:10 UTC (rev 6941)
@@ -28,45 +28,49 @@
    
    // Port 1
    always @(posedge clk)
-     if(en1_i)
-       dat1_o <= {ram3[adr1_i[AWIDTH-1:2]],
-                 ram2[adr1_i[AWIDTH-1:2]],
-                 ram1[adr1_i[AWIDTH-1:2]],
-                 ram0[adr1_i[AWIDTH-1:2]]};
+     if(en1_i) dat1_o[31:24] <= ram3[adr1_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en1_i) dat1_o[23:16] <= ram2[adr1_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en1_i) dat1_o[15:8] <= ram1[adr1_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en1_i) dat1_o[7:0] <= ram0[adr1_i[AWIDTH-1:2]];
    
    always @(posedge clk)
-     if(we1_i & en1_i)
-       begin
-         if(sel1_i[3])
-           ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24];
-         if(sel1_i[2])
-           ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16];
-         if(sel1_i[1])
-           ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8];
-         if(sel1_i[0])
-           ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0];
-       end // if (we1_i & en1_i)
+     if(we1_i & en1_i & sel1_i[3])
+       ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24];
+   always @(posedge clk)
+     if(we1_i & en1_i & sel1_i[2])
+       ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16];
+   always @(posedge clk)
+     if(we1_i & en1_i & sel1_i[1])
+       ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8];
+   always @(posedge clk)
+     if(we1_i & en1_i & sel1_i[0])
+       ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0];
    
    // Port 2
    always @(posedge clk)
-     if(en2_i)
-       dat2_o <= {ram3[adr2_i[AWIDTH-1:2]],
-                 ram2[adr2_i[AWIDTH-1:2]],
-                 ram1[adr2_i[AWIDTH-1:2]],
-                 ram0[adr2_i[AWIDTH-1:2]]};
+     if(en2_i) dat2_o[31:24] <= ram3[adr2_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en2_i) dat2_o[23:16] <= ram2[adr2_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en2_i) dat2_o[15:8] <= ram1[adr2_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en2_i) dat2_o[7:0] <= ram0[adr2_i[AWIDTH-1:2]];
    
    always @(posedge clk)
-     if(we2_i & en2_i)
-       begin
-         if(sel2_i[3])
-           ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24];
-         if(sel2_i[2])
-           ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16];
-         if(sel2_i[1])
-           ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8];
-         if(sel2_i[0])
-           ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0];
-       end // if (we2_i & en2_i)
+     if(we2_i & en2_i & sel2_i[3])
+       ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24];
+   always @(posedge clk)
+     if(we2_i & en2_i & sel2_i[2])
+       ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16];
+   always @(posedge clk)
+     if(we2_i & en2_i & sel2_i[1])
+       ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8];
+   always @(posedge clk)
+     if(we2_i & en2_i & sel2_i[0])
+       ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0];
    
 endmodule // dpram32