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[Commit-gnuradio] r6911 - in gnuradio/branches/developers/matt/u2f/openc
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From: |
matt |
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Subject: |
[Commit-gnuradio] r6911 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sim/verilog sim/verilog/CVS sw/c sw/c/CVS |
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Date: |
Wed, 14 Nov 2007 17:40:19 -0700 (MST) |
Author: matt
Date: 2007-11-14 17:40:19 -0700 (Wed, 14 Nov 2007)
New Revision: 6911
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/edk32.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
Log:
Fixes interrupt problem
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-11-15 00:37:47 UTC (rev 6910)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-11-15 00:40:19 UTC (rev 6911)
@@ -6,11 +6,11 @@
/aeMB_decode.v/1.11/Sat Nov 3 19:53:44 2007//
/aeMB_fetch.v/1.7/Sat Nov 3 19:53:44 2007//
/aeMB_regfile.v/1.19/Sat Nov 3 19:53:44 2007//
-/aeMB_bpcu.v/1.3/Sun Nov 11 19:45:40 2007//
-/aeMB_ctrl.v/1.6/Sun Nov 11 19:45:41 2007//
-/aeMB_edk32.v/1.7/Sun Nov 11 19:45:41 2007//
-/aeMB_ibuf.v/1.4/Sun Nov 11 19:45:41 2007//
/aeMB_regf.v/1.3/Sun Nov 11 19:45:41 2007//
-/aeMB_scon.v/1.5/Sun Nov 11 19:45:41 2007//
-/aeMB_xecu.v/1.6/Sun Nov 11 19:45:41 2007//
+/aeMB_bpcu.v/1.4/Wed Nov 14 23:37:06 2007//
+/aeMB_ctrl.v/1.8/Wed Nov 14 23:37:06 2007//
+/aeMB_edk32.v/1.9/Wed Nov 14 23:37:06 2007//
+/aeMB_scon.v/1.6/Wed Nov 14 23:37:06 2007//
+/aeMB_xecu.v/1.7/Wed Nov 14 23:37:06 2007//
+/aeMB_ibuf.v/1.6/Wed Nov 14 23:38:26 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
2007-11-15 00:37:47 UTC (rev 6910)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
2007-11-15 00:40:19 UTC (rev 6911)
@@ -1,4 +1,4 @@
-// $Id: aeMB_bpcu.v,v 1.3 2007/11/10 16:39:38 sybreon Exp $
+// $Id: aeMB_bpcu.v,v 1.4 2007/11/14 22:14:34 sybreon Exp $
//
// AEMB BRANCH PROGRAMME COUNTER UNIT
//
@@ -20,6 +20,9 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_bpcu.v,v $
+// Revision 1.4 2007/11/14 22:14:34 sybreon
+// Changed interrupt handling system (reported by M. Ettus).
+//
// Revision 1.3 2007/11/10 16:39:38 sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
@@ -36,10 +39,9 @@
module aeMB_bpcu (/*AUTOARG*/
// Outputs
- iwb_adr_o, rPC, rPCLNK, rBRA, rDLY, rATOM,
+ iwb_adr_o, rPC, rPCLNK, rBRA, rDLY,
// Inputs
- rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, rXCE, gclk, grst,
- gena
+ rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, gclk, grst, gena
);
parameter IW = 24;
@@ -50,14 +52,16 @@
output [31:2] rPC, rPCLNK;
output rBRA;
output rDLY;
- output [1:0] rATOM;
+ //output [1:0] rATOM;
+ //output [1:0] xATOM;
+
input [1:0] rMXALT;
input [5:0] rOPC;
input [4:0] rRD, rRA;
input [31:0] rRESULT; // ALU
input [31:0] rDWBDI; // RAM
input [31:0] rREGA;
- input [1:0] rXCE;
+ //input [1:0] rXCE;
// SYSTEM
input gclk, grst, gena;
@@ -99,8 +103,9 @@
wire fSKIP = rBRA & !rDLY;
always @(/*AUTOSENSE*/fBCC or fBRU or fRTD or rBRA or rRA or rRD
- or rXCE or xXCC)
- if (rBRA | |rXCE) begin
+ or xXCC)
+ //if (rBRA | |rXCE) begin
+ if (rBRA) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xBRA <= 1'h0;
@@ -122,19 +127,21 @@
assign iwb_adr_o = rIPC[IW-1:2];
- always @(/*AUTOSENSE*/rATOM or rBRA or rIPC or rPC or rRESULT
- or rXCE) begin
- xPCLNK <= (^rATOM) ? rPC : rPC;
- //xPCLNK <= rPC;
+ always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin
+ //xPCLNK <= (^rATOM) ? rPC : rPC;
+ xPCLNK <= rPC;
//xPC <= (^rATOM) ? rIPC : rRESULT[31:2];
xPC <= rIPC;
//xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
+ /*
case (rXCE)
2'o1: xIPC <= 30'h2;
2'o2: xIPC <= 30'h4;
2'o3: xIPC <= 30'h6;
default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
endcase // case (rXCE)
+ */
+ xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
end
// --- ATOMIC CONTROL ---------------------------------------------
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
2007-11-15 00:37:47 UTC (rev 6910)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
2007-11-15 00:40:19 UTC (rev 6911)
@@ -1,4 +1,4 @@
-// $Id: aeMB_ctrl.v,v 1.6 2007/11/10 16:39:38 sybreon Exp $
+// $Id: aeMB_ctrl.v,v 1.8 2007/11/14 23:19:24 sybreon Exp $
//
// AEMB CONTROL UNIT
//
@@ -20,6 +20,12 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_ctrl.v,v $
+// Revision 1.8 2007/11/14 23:19:24 sybreon
+// Fixed minor typo.
+//
+// Revision 1.7 2007/11/14 22:14:34 sybreon
+// Changed interrupt handling system (reported by M. Ettus).
+//
// Revision 1.6 2007/11/10 16:39:38 sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
@@ -45,11 +51,11 @@
module aeMB_ctrl (/*AUTOARG*/
// Outputs
- rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,
- dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,
+ rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,
+ fsl_stb_o, fsl_wre_o,
// Inputs
- rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
- dwb_ack_i, iwb_ack_i, iwb_dat_i, fsl_ack_i, gclk, grst, gena
+ rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
+ dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
);
// INTERNAL
//output [31:2] rPCLNK;
@@ -57,10 +63,10 @@
output [1:0] rMXSRC, rMXTGT, rMXALT;
output [2:0] rMXALU;
output [4:0] rRW;
- output rDWBSTB;
- output rFSLSTB;
+ //output rDWBSTB;
+ //output rFSLSTB;
- input [1:0] rXCE;
+ //input [1:0] rXCE;
input rDLY;
input [15:0] rIMM;
input [10:0] rALT;
@@ -69,6 +75,7 @@
input [31:2] rPC;
input rBRA;
input rMSR_IE;
+ input [31:0] xIREG;
// DATA WISHBONE
output dwb_stb_o;
@@ -77,7 +84,6 @@
// INST WISHBONE
input iwb_ack_i;
- input [31:0] iwb_dat_i;
// FSL WISHBONE
output fsl_stb_o;
@@ -94,7 +100,7 @@
wire [4:0] wRD, wRA, wRB;
wire [10:0] wALT;
- assign {wOPC, wRD, wRA, wRB, wALT} = iwb_dat_i; // FIXME: Endian
+ assign {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian
wire fSFT = (rOPC == 6'o44);
wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
@@ -183,9 +189,10 @@
wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
- always @(/*AUTOSENSE*/rBRA or rXCE or wAFWD_M or wAFWD_R or wBCC
- or wBFWD_M or wBFWD_R or wBRU or wOPC)
- if (rBRA | |rXCE) begin
+ always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M
+ or wBFWD_R or wBRU or wOPC)
+ //if (rBRA | |rXCE) begin
+ if (rBRA) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xMXALT <= 2'h0;
@@ -224,9 +231,10 @@
reg [2:0] rMXALU, xMXALU;
- always @(/*AUTOSENSE*/rBRA or rXCE or wBRA or wBSF or wDIV or wLOG
- or wMOV or wMUL or wSFT)
- if (rBRA | |rXCE) begin
+ always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
+ or wMUL or wSFT)
+ //if (rBRA | |rXCE) begin
+ if (rBRA) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xMXALU <= 3'h0;
@@ -246,7 +254,7 @@
wire fSKIP = (rBRA & !rDLY);
always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
- or fSTR or rRD or rXCE)
+ or fSTR or rRD)
if (fSKIP) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
@@ -254,6 +262,7 @@
xRW <= 5'h0;
// End of automatics
end else begin
+ /*
case (rXCE)
2'o2: xMXDST <= 2'o1;
default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
@@ -266,23 +275,29 @@
2'o2: xRW <= 5'd14;
default: xRW <= rRD;
endcase
-
+ */
+ xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
+ (fLOD | fGET) ? 2'o2 :
+ (fBRU) ? 2'o1 :
+ 2'o0;
+ xRW <= rRD;
end // else: !if(fSKIP)
// --- DATA WISHBONE ----------------------------------
+ reg rDWBSTB, xDWBSTB;
wire fDACK = !(rDWBSTB ^ dwb_ack_i);
- reg rDWBSTB, xDWBSTB;
reg rDWBWRE, xDWBWRE;
assign dwb_stb_o = rDWBSTB;
assign dwb_wre_o = rDWBWRE;
- always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
- if (fSKIP | |rXCE) begin
+ always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i)
+ //if (fSKIP | |rXCE) begin
+ if (fSKIP) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xDWBSTB <= 1'h0;
@@ -308,16 +323,17 @@
// --- FSL WISHBONE -----------------------------------
+ reg rFSLSTB, xFSLSTB;
wire fFACK = !(rFSLSTB ^ fsl_ack_i);
- reg rFSLSTB, xFSLSTB;
reg rFSLWRE, xFSLWRE;
assign fsl_stb_o = rFSLSTB;
assign fsl_wre_o = rFSLWRE;
- always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i or rXCE)
- if (fSKIP | |rXCE) begin
+ always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i)
+ //if (fSKIP | |rXCE) begin
+ if (fSKIP) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xFSLSTB <= 1'h0;
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
2007-11-15 00:37:47 UTC (rev 6910)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
2007-11-15 00:40:19 UTC (rev 6911)
@@ -1,4 +1,4 @@
-// $Id: aeMB_edk32.v,v 1.7 2007/11/10 16:39:38 sybreon Exp $
+// $Id: aeMB_edk32.v,v 1.9 2007/11/14 23:19:24 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core
//
@@ -20,6 +20,12 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_edk32.v,v $
+// Revision 1.9 2007/11/14 23:19:24 sybreon
+// Fixed minor typo.
+//
+// Revision 1.8 2007/11/14 22:14:34 sybreon
+// Changed interrupt handling system (reported by M. Ettus).
+//
// Revision 1.7 2007/11/10 16:39:38 sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
@@ -51,8 +57,8 @@
iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o, fsl_dat_o, fsl_adr_o,
dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
// Inputs
- sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
- fsl_ack_i, dwb_dat_i, dwb_ack_i
+ sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
+ dwb_ack_i, sys_clk_i, sys_rst_i
);
// Bus widths
parameter IW = 32; /// Instruction bus address width
@@ -78,29 +84,21 @@
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
- input dwb_ack_i; // To scon of aeMB_scon.v, ...
+ input dwb_ack_i; // To ctrl of aeMB_ctrl.v
input [31:0] dwb_dat_i; // To regf of
aeMB_regf.v
- input fsl_ack_i; // To scon of aeMB_scon.v, ...
+ input fsl_ack_i; // To ctrl of aeMB_ctrl.v
input [31:0] fsl_dat_i; // To regf of
aeMB_regf.v
- input iwb_ack_i; // To scon of aeMB_scon.v, ...
- input [31:0] iwb_dat_i; // To ibuf of
aeMB_ibuf.v, ...
- input sys_clk_i; // To scon of aeMB_scon.v
- input sys_int_i; // To scon of aeMB_scon.v
- input sys_rst_i; // To scon of aeMB_scon.v
+ input iwb_ack_i; // To ibuf of aeMB_ibuf.v, ...
+ input [31:0] iwb_dat_i; // To ibuf of
aeMB_ibuf.v
+ input sys_int_i; // To ibuf of aeMB_ibuf.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
- wire gclk; // From scon of
aeMB_scon.v
- wire gena; // From scon of
aeMB_scon.v
- wire grst; // From scon of
aeMB_scon.v
wire [10:0] rALT; // From ibuf of aeMB_ibuf.v
- wire [1:0] rATOM; // From bpcu of aeMB_bpcu.v
wire rBRA; // From bpcu of
aeMB_bpcu.v
wire rDLY; // From bpcu of
aeMB_bpcu.v
wire [31:0] rDWBDI; // From regf of aeMB_regf.v
wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v
- wire rDWBSTB; // From ctrl of
aeMB_ctrl.v
- wire rFSLSTB; // From ctrl of
aeMB_ctrl.v
wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v
wire rMSR_BIP; // From xecu of
aeMB_xecu.v
wire rMSR_IE; // From xecu of
aeMB_xecu.v
@@ -120,32 +118,16 @@
wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
- wire [1:0] rXCE; // From scon of aeMB_scon.v
+ wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v
// End of automatics
-
- aeMB_scon
- scon (/*AUTOINST*/
- // Outputs
- .rXCE (rXCE[1:0]),
- .grst (grst),
- .gclk (gclk),
- .gena (gena),
- // Inputs
- .rOPC (rOPC[5:0]),
- .rATOM (rATOM[1:0]),
- .rDWBSTB (rDWBSTB),
- .rFSLSTB (rFSLSTB),
- .dwb_ack_i (dwb_ack_i),
- .iwb_ack_i (iwb_ack_i),
- .fsl_ack_i (fsl_ack_i),
- .rMSR_IE (rMSR_IE),
- .rMSR_BIP (rMSR_BIP),
- .rBRA (rBRA),
- .rDLY (rDLY),
- .sys_clk_i (sys_clk_i),
- .sys_rst_i (sys_rst_i),
- .sys_int_i (sys_int_i));
+ input sys_clk_i;
+ input sys_rst_i;
+
+ wire grst = sys_rst_i;
+ wire gclk = sys_clk_i;
+ wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^
fsl_ack_i) | !iwb_ack_i);
+
aeMB_ibuf
ibuf (/*AUTOINST*/
// Outputs
@@ -156,12 +138,15 @@
.rALT (rALT[10:0]),
.rOPC (rOPC[5:0]),
.rSIMM (rSIMM[31:0]),
+ .xIREG (xIREG[31:0]),
.iwb_stb_o (iwb_stb_o),
// Inputs
.rBRA (rBRA),
- .rXCE (rXCE[1:0]),
+ .rMSR_IE (rMSR_IE),
+ .rMSR_BIP (rMSR_BIP),
.iwb_dat_i (iwb_dat_i[31:0]),
.iwb_ack_i (iwb_ack_i),
+ .sys_int_i (sys_int_i),
.gclk (gclk),
.grst (grst),
.gena (gena));
@@ -175,14 +160,11 @@
.rMXALT (rMXALT[1:0]),
.rMXALU (rMXALU[2:0]),
.rRW (rRW[4:0]),
- .rDWBSTB (rDWBSTB),
- .rFSLSTB (rFSLSTB),
.dwb_stb_o (dwb_stb_o),
.dwb_wre_o (dwb_wre_o),
.fsl_stb_o (fsl_stb_o),
.fsl_wre_o (fsl_wre_o),
// Inputs
- .rXCE (rXCE[1:0]),
.rDLY (rDLY),
.rIMM (rIMM[15:0]),
.rALT (rALT[10:0]),
@@ -193,9 +175,9 @@
.rPC (rPC[31:2]),
.rBRA (rBRA),
.rMSR_IE (rMSR_IE),
+ .xIREG (xIREG[31:0]),
.dwb_ack_i (dwb_ack_i),
.iwb_ack_i (iwb_ack_i),
- .iwb_dat_i (iwb_dat_i[31:0]),
.fsl_ack_i (fsl_ack_i),
.gclk (gclk),
.grst (grst),
@@ -209,7 +191,6 @@
.rPCLNK (rPCLNK[31:2]),
.rBRA (rBRA),
.rDLY (rDLY),
- .rATOM (rATOM[1:0]),
// Inputs
.rMXALT (rMXALT[1:0]),
.rOPC (rOPC[5:0]),
@@ -218,7 +199,6 @@
.rRESULT (rRESULT[31:0]),
.rDWBDI (rDWBDI[31:0]),
.rREGA (rREGA[31:0]),
- .rXCE (rXCE[1:0]),
.gclk (gclk),
.grst (grst),
.gena (gena));
@@ -260,7 +240,6 @@
.rMSR_IE (rMSR_IE),
.rMSR_BIP (rMSR_BIP),
// Inputs
- .rXCE (rXCE[1:0]),
.rREGA (rREGA[31:0]),
.rREGB (rREGB[31:0]),
.rMXSRC (rMXSRC[1:0]),
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
2007-11-15 00:37:47 UTC (rev 6910)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
2007-11-15 00:40:19 UTC (rev 6911)
@@ -1,4 +1,4 @@
-// $Id: aeMB_ibuf.v,v 1.4 2007/11/10 16:39:38 sybreon Exp $
+// $Id: aeMB_ibuf.v,v 1.6 2007/11/14 23:39:51 sybreon Exp $
//
// AEMB INSTRUCTION BUFFER
//
@@ -20,6 +20,12 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_ibuf.v,v $
+// Revision 1.6 2007/11/14 23:39:51 sybreon
+// Fixed interrupt signal synchronisation.
+//
+// Revision 1.5 2007/11/14 22:14:34 sybreon
+// Changed interrupt handling system (reported by M. Ettus).
+//
// Revision 1.4 2007/11/10 16:39:38 sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
@@ -39,9 +45,10 @@
module aeMB_ibuf (/*AUTOARG*/
// Outputs
- rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, iwb_stb_o,
+ rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, iwb_stb_o,
// Inputs
- rBRA, rXCE, iwb_dat_i, iwb_ack_i, gclk, grst, gena
+ rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
+ grst, gena
);
// INTERNAL
output [15:0] rIMM;
@@ -49,8 +56,12 @@
output [10:0] rALT;
output [5:0] rOPC;
output [31:0] rSIMM;
+ output [31:0] xIREG;
+
input rBRA;
- input [1:0] rXCE;
+ //input [1:0] rXCE;
+ input rMSR_IE;
+ input rMSR_BIP;
// INST WISHBONE
output iwb_stb_o;
@@ -58,6 +69,9 @@
input iwb_ack_i;
// SYSTEM
+ input sys_int_i;
+
+ // SYSTEM
input gclk, grst, gena;
reg [15:0] rIMM;
@@ -72,17 +86,60 @@
assign iwb_stb_o = 1'b1;
reg [31:0] rSIMM, xSIMM;
- wire fIMM = (rOPC == 6'o54);
+
+ wire [31:0] wXCEOP = 32'hB9CE0008;
+ wire [31:0] wINTOP = 32'hB9CE0010;
+ wire [31:0] wBRKOP = 32'hB9CE0018;
+ wire [31:0] wBRAOP = 32'h88000000;
+ wire [31:0] wIREG = {rOPC, rRD, rRA, rRB, rALT};
reg [31:0] xIREG;
- // DELAY SLOT
- always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or rXCE or wIDAT) begin
- xIREG <= (rBRA | |rXCE) ? 32'h88000000 : wIDAT;
- xSIMM <= (!fIMM | rBRA | |rXCE) ? { {(16){wIDAT[15]}}, wIDAT[15:0]} :
{rIMM, wIDAT[15:0]};
+
+ // --- INTERRUPT LATCH --------------------------------------
+ // Debounce and latch onto the positive edge. This is independent
+ // of the pipeline so that stalls do not affect it.
+
+ reg rFINT;
+ reg [1:0] rDINT;
+ //wire wSHOT = rDINT[0] & !rDINT[1] & sys_int_i;
+ //wire wSHOT = !rDINT[0] & sys_int_i;
+ wire wSHOT = (rDINT == 2'o1);
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rDINT <= 2'h0;
+ rFINT <= 1'h0;
+ // End of automatics
+ end else if (rMSR_IE) begin
+ rDINT <= #1 {rDINT[0], sys_int_i};
+ rFINT <= #1 (wIREG == wINTOP) ? 1'b0 : (rFINT | wSHOT);
+ end
+
+ wire fIMM = (rOPC == 6'o54);
+ wire fRTD = (rOPC == 6'o55);
+ wire fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56));
+ wire fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57));
+
+ // --- DELAY SLOT -------------------------------------------
+
+ always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT
+ or wBRAOP or wIDAT or wINTOP) begin
+ xIREG <= (rBRA) ? wBRAOP :
+ (!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP :
+ wIDAT;
end
+
+ always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin
+ //xSIMM <= (!fIMM | rBRA | |rXCE) ? { {(16){wIDAT[15]}}, wIDAT[15:0]} :
{rIMM, wIDAT[15:0]};
+ xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} :
+ {rIMM, wIDAT[15:0]};
+ end
- // Synchronous
+ // --- PIPELINE --------------------------------------------
+
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
2007-11-15 00:37:47 UTC (rev 6910)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
2007-11-15 00:40:19 UTC (rev 6911)
@@ -1,4 +1,4 @@
-// $Id: aeMB_scon.v,v 1.5 2007/11/10 16:39:38 sybreon Exp $
+// $Id: aeMB_scon.v,v 1.6 2007/11/14 22:14:34 sybreon Exp $
//
// AEMB SYSTEM CONTROL UNIT
//
@@ -20,6 +20,9 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_scon.v,v $
+// Revision 1.6 2007/11/14 22:14:34 sybreon
+// Changed interrupt handling system (reported by M. Ettus).
+//
// Revision 1.5 2007/11/10 16:39:38 sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
@@ -42,16 +45,17 @@
module aeMB_scon (/*AUTOARG*/
// Outputs
- rXCE, grst, gclk, gena,
+ grst, gclk, gena,
// Inputs
- rOPC, rATOM, rDWBSTB, rFSLSTB, dwb_ack_i, iwb_ack_i, fsl_ack_i,
- rMSR_IE, rMSR_BIP, rBRA, rDLY, sys_clk_i, sys_rst_i, sys_int_i
+ rOPC, rDWBSTB, rFSLSTB, dwb_ack_i, iwb_ack_i, fsl_ack_i, rMSR_IE,
+ rMSR_BIP, rBRA, rDLY, sys_clk_i, sys_rst_i, sys_int_i
);
// INTERNAL
- output [1:0] rXCE;
+ //output [1:0] rXCE;
input [5:0] rOPC;
- input [1:0] rATOM;
+ //input [1:0] rATOM;
+ //input [1:0] xATOM;
input rDWBSTB;
input rFSLSTB;
@@ -76,6 +80,8 @@
// --- INTERRUPT LATCH --------------------------------------
// Debounce and latch onto the positive edge. This is independent
// of the pipeline so that stalls do not affect it.
+
+ wire [1:0] rXCE;
reg rFINT;
reg [1:0] rDINT;
@@ -90,7 +96,7 @@
// End of automatics
end else if (rMSR_IE) begin
rDINT <= #1 {rDINT[0], sys_int_i};
- rFINT <= (rXCE == 2'o2) ? 1'b0 : (rFINT | wSHOT);
+ rFINT <= ((rXCE == 2'o2) & gena) ? 1'b0 : (rFINT | wSHOT);
end
@@ -98,12 +104,15 @@
// Process the independent priority flags to determine which
// interrupt/exception/break to handle.
- reg [1:0] rXCE;
+ wire [1:0] rATOM;
+
+ reg [1:0] xXCE;
reg rENA;
- wire fINT = rENA & ^rATOM & !rMSR_BIP & rMSR_IE & rFINT;
+ //wire fINT = rENA & ^rATOM & !rMSR_BIP & rMSR_IE & rFINT;
+ wire fINT = ^rATOM & !rMSR_BIP & rMSR_IE & rFINT;
always @(/*AUTOSENSE*/fINT)
- rXCE <= (fINT) ? 2'o2 : 2'o0;
+ xXCE <= (fINT) ? 2'o0 : 2'o0;
always @(posedge gclk)
if (grst) begin
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
2007-11-15 00:37:47 UTC (rev 6910)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
2007-11-15 00:40:19 UTC (rev 6911)
@@ -1,4 +1,4 @@
-// $Id: aeMB_xecu.v,v 1.6 2007/11/10 16:39:38 sybreon Exp $
+// $Id: aeMB_xecu.v,v 1.7 2007/11/14 22:14:34 sybreon Exp $
//
// AEMB MAIN EXECUTION ALU
//
@@ -20,6 +20,9 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_xecu.v,v $
+// Revision 1.7 2007/11/14 22:14:34 sybreon
+// Changed interrupt handling system (reported by M. Ettus).
+//
// Revision 1.6 2007/11/10 16:39:38 sybreon
// Upgraded license to LGPLv3.
// Significant performance optimisations.
@@ -48,8 +51,8 @@
dwb_adr_o, dwb_sel_o, fsl_adr_o, rRESULT, rDWBSEL, rMSR_IE,
rMSR_BIP,
// Inputs
- rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY,
- rALT, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
+ rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT,
+ rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
);
parameter DW=32;
@@ -68,7 +71,7 @@
output [3:0] rDWBSEL;
output rMSR_IE;
output rMSR_BIP;
- input [1:0] rXCE;
+ //input [1:0] rXCE;
input [31:0] rREGA, rREGB;
input [1:0] rMXSRC, rMXTGT;
input [4:0] rRA, rRB;
@@ -256,8 +259,9 @@
wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
- or rOPA or rRES_ADDC or rRES_SFTC or rXCE)
- if (fSKIP | |rXCE) begin
+ or rOPA or rRES_ADDC or rRES_SFTC)
+ //if (fSKIP | |rXCE) begin
+ if (fSKIP) begin
xMSR_C <= rMSR_C;
end else
case (rMXALU)
@@ -273,10 +277,11 @@
// IE/BIP/BE
wire fRTID = (rOPC == 6'o55) & rRD[0];
wire fRTBD = (rOPC == 6'o55) & rRD[1];
- wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA[4:2] ==
3'o3);
+ wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
+ wire fXCE = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
- always @(/*AUTOSENSE*/fMTS or fRTID or rMSR_IE or rOPA or rXCE)
- xMSR_IE <= (rXCE == 2'o2) ? 1'b0 :
+ always @(/*AUTOSENSE*/fMTS or fRTID or fXCE or rMSR_IE or rOPA)
+ xMSR_IE <= (fXCE) ? 1'b0 :
(fRTID) ? 1'b1 :
(fMTS) ? rOPA[1] :
rMSR_IE;
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
2007-11-15 00:37:47 UTC (rev 6910)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
2007-11-15 00:40:19 UTC (rev 6911)
@@ -1,4 +1,4 @@
/utestbench.v/1.1/Fri Apr 13 13:02:34 2007//
/testbench.v/1.6/Sat Nov 3 19:53:44 2007//
-/edk32.v/1.6/Wed Nov 14 17:40:27 2007//
+/edk32.v/1.7/Wed Nov 14 23:37:06 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/edk32.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/edk32.v
2007-11-15 00:37:47 UTC (rev 6910)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/edk32.v
2007-11-15 00:40:19 UTC (rev 6911)
@@ -1,25 +1,29 @@
-// $Id: edk32.v,v 1.6 2007/11/13 23:37:28 sybreon Exp $
+// $Id: edk32.v,v 1.7 2007/11/14 22:11:41 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core TEST
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
//
-// This library is free software; you can redistribute it and/or
-// modify it under the terms of the GNU Lesser General Public License
-// as published by the Free Software Foundation; either version 2.1 of
-// the License, or (at your option) any later version.
+// This file is part of AEMB.
//
-// This library is distributed in the hope that it will be useful, but
-// WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-// Lesser General Public License for more details.
-//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+// Public License for more details.
+//
// You should have received a copy of the GNU Lesser General Public
-// License along with this library; if not, write to the Free Software
-// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-// USA
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: edk32.v,v $
+// Revision 1.7 2007/11/14 22:11:41 sybreon
+// Added posedge/negedge bus interface.
+// Modified interrupt test system.
+//
// Revision 1.6 2007/11/13 23:37:28 sybreon
// Updated simulation to also check BRI 0x00 instruction.
//
@@ -59,6 +63,7 @@
initial begin
//$dumpfile("dump.vcd");
//$dumpvars(1,dut);
+ //$dumpvars(1,dut.scon);
end
initial begin
@@ -69,7 +74,7 @@
sys_rst_i = 1;
sys_int_i = 0;
sys_exc_i = 0;
- #30 sys_rst_i = 0;
+ #50 sys_rst_i = 0;
end
initial fork
@@ -104,22 +109,74 @@
wire [3:0] dwb_sel_o;
wire [31:0] dwb_dat_o;
wire [15:2] dwb_adr_o;
- wire [31:0] dwb_dat_t;
+ wire [31:0] dwb_dat_t;
+
+ initial begin
+ dwb_ack_i = 0;
+ iwb_ack_i = 0;
+ fsl_ack_i = 0;
+ end
assign
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
assign
{iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
assign {dwb_dat_t} = ram[dwb_adr_o];
assign fsl_dat_i = fsl_adr_o;
+
+//`define POSEDGE
+`ifdef POSEDGE
+ always @(posedge sys_clk_i)
+ if (sys_rst_i) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ dwb_ack_i <= 1'h0;
+ fsl_ack_i <= 1'h0;
+ iwb_ack_i <= 1'h0;
+ // End of automatics
+ end else begin
+ iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;
+ dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
+ fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
+ end
+
+ always @(posedge sys_clk_i) begin
+ iadr <= #1 iwb_adr_o;
+ dadr <= #1 dwb_adr_o;
+
+ if (dwb_we_o & dwb_stb_o) begin
+ case (dwb_sel_o)
+ 4'h1: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]};
+ 4'h2: ram[dwb_adr_o] <=
{dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]};
+ 4'h4: ram[dwb_adr_o] <=
{dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_t[7:0]};
+ 4'h8: ram[dwb_adr_o] <= {dwb_dat_t[31:8],dwb_dat_o[31:24]};
+ 4'h3: ram[dwb_adr_o] <=
{dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_t[15:0]};
+ 4'hC: ram[dwb_adr_o] <=
{dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_o[31:24]};
+ 4'hF: ram[dwb_adr_o] <=
{dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]};
+ endcase // case (dwb_sel_o)
+ end // if (dwb_we_o & dwb_stb_o)
+ end // always @ (negedge sys_clk_i)
+
+`else // !`ifdef POSEDGE
+
+ always @(negedge sys_clk_i)
+ if (sys_rst_i) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ dwb_ack_i <= 1'h0;
+ fsl_ack_i <= 1'h0;
+ iwb_ack_i <= 1'h0;
+ // End of automatics
+ end else begin
+ iwb_ack_i <= #1 iwb_stb_o;
+ dwb_ack_i <= #1 dwb_stb_o;
+ fsl_ack_i <= #1 fsl_stb_o;
+ end
+
always @(negedge sys_clk_i) begin
- iwb_ack_i <= #1 iwb_stb_o;
- dwb_ack_i <= #1 dwb_stb_o;
- fsl_ack_i <= #1 fsl_stb_o;
+ iadr <= #1 iwb_adr_o;
+ dadr <= #1 dwb_adr_o;
- iadr <= #1 iwb_adr_o;
- dadr <= dwb_adr_o;
-
if (dwb_we_o & dwb_stb_o) begin
case (dwb_sel_o)
4'h1: ram[dwb_adr_o] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]};
@@ -132,6 +189,9 @@
endcase // case (dwb_sel_o)
end // if (dwb_we_o & dwb_stb_o)
end // always @ (negedge sys_clk_i)
+
+`endif // !`ifdef POSEDGE
+
integer i;
initial begin
@@ -163,7 +223,10 @@
$finish;
end
if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
- if (|dut.rXCE) svc = 1;
+ if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin
+ svc = 1;
+ //$display("\nLATENCY: ", ($stime - inttime)/10);
+ end
// Pass/Fail Monitors
if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
@@ -188,13 +251,13 @@
// DECODE
$writeh ("\t");
-
+ /*
case (dut.bpcu.rATOM)
2'o2, 2'o1: $write("/");
2'o0, 2'o3: $write("\\");
endcase // case (dut.bpcu.rATOM)
+ */
-
case ({dut.rBRA, dut.rDLY})
2'b00: $write(" ");
2'b01: $write(".");
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
2007-11-15 00:37:47 UTC (rev 6910)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
2007-11-15 00:40:19 UTC (rev 6911)
@@ -1,2 +1,2 @@
-/aeMB_testbench.c/1.9/Sun Nov 11 19:45:41 2007//
+/aeMB_testbench.c/1.11/Wed Nov 14 23:39:58 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
2007-11-15 00:37:47 UTC (rev 6910)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
2007-11-15 00:40:19 UTC (rev 6911)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_testbench.c,v 1.9 2007/11/09 20:51:53 sybreon Exp $
+ * $Id: aeMB_testbench.c,v 1.11 2007/11/14 23:41:06 sybreon Exp $
*
* AEMB Function Verification C Testbench
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,12 @@
*
* HISTORY
* $Log: aeMB_testbench.c,v $
+ * Revision 1.11 2007/11/14 23:41:06 sybreon
+ * Fixed minor interrupt test typo.
+ *
+ * Revision 1.10 2007/11/14 22:12:02 sybreon
+ * Added interrupt test routine.
+ *
* Revision 1.9 2007/11/09 20:51:53 sybreon
* Added GET/PUT support through a FSL bus.
*
@@ -64,25 +70,30 @@
*/
// void int_service (void) __attribute__((save_volatiles));
void int_handler (void) __attribute__ ((interrupt_handler));
-
+int service;
void int_enable()
{
- asm ("mfs r14, rmsr");
- asm ("ori r14, r14, 0x0002");
- asm ("mts rmsr, r14");
+ int tmp;
+ service = 0;
+ asm ("mfs %0, rmsr;" : "=r" (tmp));
+ tmp = tmp | 0x02;
+ asm ("mts rmsr, %0;" :: "r" (tmp));
}
void int_disable()
{
- asm ("mfs r14, rmsr");
- asm ("andi r14, r14, 0x00FD");
- asm ("mts rmsr, r14");
+ int tmp;
+ service = 1;
+ asm ("mfs %0, rmsr;" : "=r" (tmp));
+ tmp = tmp & 0xFD;
+ asm ("mts rmsr, %0;" :: "r" (tmp));
}
void int_service()
{
int* pio = (int*)0xFFFFFFFC;
*pio = 0x52544E49; // "INTR"
+ service = -1;
}
void int_handler()
@@ -90,6 +101,18 @@
int_service();
}
+/**
+ INTERRUPT TEST ROUTINE
+*/
+int int_test ()
+{
+ // Delay loop until hardware interrupt triggers
+ int i;
+ for (i=0; i < 777; i++) {
+ asm volatile ("nop;");
+ }
+ return (service == 0) ? -1 : 1;
+}
/**
FIBONACCI TEST
@@ -309,12 +332,15 @@
// Number of each test to run
int max = 10;
+ // Enable Global Interrupts
+ int_enable();
+
+ // INT TEST
+ if (int_test() == -1) { *mpi = 0x4641494C; }
+
// FSL TEST
if (fsl_test() == -1) { *mpi = 0x4641494C; }
- // Enable Global Interrupts
- int_enable();
-
// Fibonacci Test
if (fib_test(max) == -1) { *mpi = 0x4641494C; }
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- [Commit-gnuradio] r6911 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sim/verilog sim/verilog/CVS sw/c sw/c/CVS,
matt <=