[Commit-gnuradio] r6907 - gnuradio/branches/developers/matt/u2f/firmware

[eb]

Author: eb
Date: 2007-11-14 17:06:39 -0700 (Wed, 14 Nov 2007)
New Revision: 6907

Modified:
   gnuradio/branches/developers/matt/u2f/firmware/eth_mac.c
   gnuradio/branches/developers/matt/u2f/firmware/hal_uart.c
   gnuradio/branches/developers/matt/u2f/firmware/memory_map.h
Log:
uart stuff

Modified: gnuradio/branches/developers/matt/u2f/firmware/eth_mac.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/eth_mac.c    2007-11-14 
23:28:53 UTC (rev 6906)
+++ gnuradio/branches/developers/matt/u2f/firmware/eth_mac.c    2007-11-15 
00:06:39 UTC (rev 6907)
@@ -26,12 +26,6 @@
 
 #define PHY_ADDR 1
 
-inline static bool 
-simulation_p(void)
-{
-  return buffer_pool_status->sim_mode;
-}
-
 void 
 eth_mac_init(void)
 {
@@ -58,7 +52,7 @@
 int
 eth_mac_miim_read(int addr)
 {
-  if (simulation_p()){
+  if (hwconfig_simulation_p()){
     switch(addr){
     case PHY_LINK_AN:
       return LANSR_MASTER | LANSR_LINK_GOOD | LANSR_SPEED_1000;
@@ -92,7 +86,7 @@
 int
 eth_mac_miim_read_status(void)
 {
-  if (simulation_p())
+  if (hwconfig_simulation_p())
     return 0;
 
   return eth_mac->miistatus;

Modified: gnuradio/branches/developers/matt/u2f/firmware/hal_uart.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/hal_uart.c   2007-11-14 
23:28:53 UTC (rev 6906)
+++ gnuradio/branches/developers/matt/u2f/firmware/hal_uart.c   2007-11-15 
00:06:39 UTC (rev 6907)
@@ -30,18 +30,15 @@
 //#define CALC_DIVISOR(rate) (WISHBONE_CLK_RATE / ((rate) * 16))
 
 #define NSPEEDS 5
+#define        MAX_WB_DIV 4
 
 static const uint16_t
-divisor_table[NSPEEDS] = {     // KLUDGE fragile
-#if   WISHBONE_CLK_RATE == 25000000
-  163,  81, 41, 27, 13
-#elif WISHBONE_CLK_RATE == 33333333
-  217, 109, 54, 36, 17
-#elif WISHBONE_CLK_RATE == 50000000
-  326, 163, 81, 54, 26
-#else
-#error "Unexpected WISHBONE_CLK_RATE"
-#endif
+divisor_table[MAX_WB_DIV+1][NSPEEDS] = {
+  { 2, 2, 2, 2, 2},            // 0: can't happen
+  { 651, 326, 163, 109, 52},   // 1: 100 MHz
+  { 326, 163,  81,  54, 26 },  // 2:  50 MHz
+  { 217, 109,  54,  36, 17 },  // 3:  33.3333 MHz
+  { 163,  81,  41,  27, 13 },  // 4:  25 MHz
 };
 
 static hal_uart_config_t current_config;
@@ -67,12 +64,22 @@
 void 
 hal_uart_set_config(const hal_uart_config_t *c)
 {
+  uint16_t divisor;
+
   if (c->speed >= NSPEEDS)
     return;
 
   current_config = *c;
 
-  uint16_t divisor = divisor_table[current_config.speed];
+  if (hwconfig_simulation_p()) // if we're simulating, go fast ;)
+    divisor = 2;
+  else {
+    int t = hwconfig_wishbone_divisor();
+    if (t > MAX_WB_DIV)
+      t = MAX_WB_DIV;
+    divisor = divisor_table[t][current_config.speed];
+  }
+
   u->lcr = UART_LCR_8N1 | UART_LCR_DLAB;  // enable access to divisor regs
   u->ier = (divisor >> 8);      // write MSB first
   u->data = (divisor & 0xff);  // then LSB

Modified: gnuradio/branches/developers/matt/u2f/firmware/memory_map.h
===================================================================
--- gnuradio/branches/developers/matt/u2f/firmware/memory_map.h 2007-11-14 
23:28:53 UTC (rev 6906)
+++ gnuradio/branches/developers/matt/u2f/firmware/memory_map.h 2007-11-15 
00:06:39 UTC (rev 6907)
@@ -23,7 +23,6 @@
 #define INCLUDED_MEMORY_MAP_H
 
 #define MASTER_CLK_RATE        100000000               // 100 MHz
-#define WISHBONE_CLK_RATE      (MASTER_CLK_RATE / 3)   // 33.333 MHz
 
 
 ////////////////////////////////////////////////////////////////
@@ -165,7 +164,7 @@
 typedef struct {
   volatile unsigned last_line[8];     // last line xfer'd in buffer
   volatile unsigned status;          // error and done flags
-  volatile unsigned sim_mode;        // LSB is 1 if we're in simulation
+  volatile unsigned hw_config;       // see below
 } buffer_pool_status_t;
 
 #define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE)
@@ -187,7 +186,30 @@
 #define        BPS_ERROR_6     0x4000        // buffer 6 xfer had error
 #define        BPS_ERROR_7     0x8000        // buffer 7 xfer had error
 
+// The hw_config register
 
+#define        HWC_SIMULATION          0x80000000
+#define        HWC_WB_CLK_DIV_MASK     0x0000000f
+
+/*!
+ * \brief return non-zero if we're running under the simulator
+ */
+inline static int
+hwconfig_simulation_p(void)
+{
+  return buffer_pool_status->hw_config & HWC_SIMULATION;
+}
+
+/*!
+ * \brief Return Wishbone Clock divisor.
+ * The processor runs at the Wishbone Clock rate which is MASTER_CLK_RATE / 
divisor.
+ */
+inline static int
+hwconfig_wishbone_divisor(void)
+{
+  return buffer_pool_status->hw_config & HWC_WB_CLK_DIV_MASK;
+}
+
 ///////////////////////////////////////////////////
 // Ethernet Core, Slave 6