[Commit-gnuradio] r6901 - in gnuradio/branches/developers/matt/u2f/top: u2_basic u2_sim

[matt]

Author: matt
Date: 2007-11-14 13:01:11 -0700 (Wed, 14 Nov 2007)
New Revision: 6901

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
   gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
Log:
tell the system what the clock divider is


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-11-14 17:44:54 UTC (rev 6900)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-11-14 20:01:11 UTC (rev 6901)
@@ -119,7 +119,8 @@
    output uart_tx_o, 
    input uart_rx_i,
    output uart_baud_o,
-   input sim_mode
+   input sim_mode,
+   input [3:0] clock_divider
    );
    
    wire [7:0]  set_addr;
@@ -345,7 +346,7 @@
       
       
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
       
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
-      .word08(status),.word09({31'b0,sim_mode}),.word10(),.word11(),
+      
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(),.word11(),
       .word12(),.word13(),.word14(),.word15()
       );
 

Modified: gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v       
2007-11-14 17:44:54 UTC (rev 6900)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v       
2007-11-14 20:01:11 UTC (rev 6901)
@@ -126,31 +126,30 @@
    initial clk_to_mac = 0;
    always #4 clk_to_mac = ~clk_to_mac;
    
-   wire        div_clk;
-   reg [2:0]   div_ctr = 0;
+   reg                div_clk;
+   reg [7:0]   div_ctr = 0;
    
    assign      dsp_clk = clock_ready ? clk_fpga : aux_clk;
    assign      wb_clk = div_clk;
 
-   /*  // Div by 4
+   localparam  clock_divider = 3;
+
    always @(posedge dsp_clk or negedge dsp_clk)
-     if(div_ctr==7)
+     if(div_ctr == (2*clock_divider-1))
        div_ctr <= 0;
      else
        div_ctr <= div_ctr + 1;
-   assign      div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2) | 
(div_ctr == 3);
-    */
 
-   // Div by 3
-   always @(posedge dsp_clk or negedge dsp_clk)
-     if(div_ctr==5)
-       div_ctr <= 0;
+   always @*
+     if(clock_divider == 3)
+       div_clk <= (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2);
      else
-       div_ctr <= div_ctr + 1;
-   assign      div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2);
-   
+       div_clk <= (div_ctr < clock_divider) ? 1'b1 : 1'b0;
+     
    initial
      $monitor($time, ,clock_ready);
+
+   always #1000000 $monitor("Time in ns ",$time);
    
    initial begin
       $dumpfile("u2_sim_top.lxt");
@@ -268,7 +267,8 @@
                     .uart_tx_o         (uart_tx_o),
                     .uart_rx_i         (uart_rx_i),
                     .uart_baud_o       (uart_baud_o),
-                    .sim_mode          (1'b1)
+                    .sim_mode          (1'b1),
+                    .clock_divider     (clock_divider)
                     );
 
    // Experimental printf-like function