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[Commit-gnuradio] r6896 - in gnuradio/branches/developers/zhuochen/inban
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From: |
zhuochen |
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Subject: |
[Commit-gnuradio] r6896 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib toplevel/usrp_inband_usb |
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Date: |
Wed, 14 Nov 2007 08:19:33 -0700 (MST) |
Author: zhuochen
Date: 2007-11-14 08:19:32 -0700 (Wed, 14 Nov 2007)
New Revision: 6896
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
Work in progress on full USB packets
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
2007-11-14 10:32:57 UTC (rev 6895)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
2007-11-14 15:19:32 UTC (rev 6896)
@@ -48,13 +48,17 @@
wire [8:0] chan_used;
wire [31:0] true_rssi;
wire [4:0] true_channel;
+ wire ready_to_send;
assign debugbus = {state, chan_empty[0], underrun[0], check_next[0],
have_space, rd_select[0]};
assign chan_used = chan_usedw[8:0];
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
((rd_select[0]) ?
rssi_1:rssi_0);
- assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next -
4'd1});
+ assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next -
4'd1});
+ assign ready_to_send = (chan_used == 9'd504) ||
+ ((rd_select == NUM_CHAN)&&(chan_used > 0));
+
always @(posedge rxclk)
begin
if (reset)
@@ -76,7 +80,10 @@
if (have_space)
begin
//transmit if the usb buffer
have space
- state <= #1 `HEADER1;
+ //check if we should send
+ if (ready_to_send)
+ state <= #1 `HEADER1;
+
overrun[check_next] <= 0;
end
else
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-11-14 10:32:57 UTC (rev 6895)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-11-14 15:19:32 UTC (rev 6896)
@@ -1,25 +1,57 @@
module register_io
- ( // System
- input clk, input reset, input wire [1:0] enable,
- input wire [6:0] addr, input wire [31:0] datain,
- output reg [31:0] dataout, output wire [15:0] debugbus,
- output reg [6:0] addr_wr, output reg [31:0] data_wr, output wire
strobe_wr,
- // output for rssi
- output wire [31:0] threshhold, output wire [31:0] rssi_wait,
- // Input data lines
- input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0]
rssi_2, input wire [31:0] rssi_3,
- input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0]
reg_2, input wire [15:0] reg_3,
- input wire [11:0] atr_tx_delay, input wire [11:0] atr_rx_delay, input
wire [7:0] master_controls,
- input wire [3:0] debug_en, input wire [7:0] interp_rate, input wire [7:0]
decim_rate,
- input wire [15:0] atr_mask_0, input wire [15:0] atr_txval_0, input wire
[15:0] atr_rxval_0,
- input wire [15:0] atr_mask_1, input wire [15:0] atr_txval_1, input wire
[15:0] atr_rxval_1,
- input wire [15:0] atr_mask_2, input wire [15:0] atr_txval_2, input wire
[15:0] atr_rxval_2,
- input wire [15:0] atr_mask_3, input wire [15:0] atr_txval_3, input wire
[15:0] atr_rxval_3,
- input wire [7:0] txa_refclk, input wire [7:0] txb_refclk, input wire
[7:0] rxa_refclk, input wire [7:0] rxb_refclk,
- input wire [7:0] misc, input wire [31:0] txmux);
-
- // assigning wires according to their address
- wire [31:0] bundle[43:0];
+ (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr,
strobe_wr,
+ rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1,
reg_2, reg_3,
+ atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate,
decim_rate,
+ atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1,
atr_rxval_1,
+ atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3,
atr_rxval_3,
+ txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);
+
+ input clk;
+ input reset;
+ input wire [1:0] enable;
+ input wire [6:0] addr;
+ input wire [31:0] datain;
+ output reg [31:0] dataout;
+ output wire [15:0] debugbus;
+ output reg [6:0] addr_wr;
+ output reg [31:0] data_wr;
+ output wire strobe_wr;
+ input wire [31:0] rssi_0;
+ input wire [31:0] rssi_1;
+ input wire [31:0] rssi_2;
+ input wire [31:0] rssi_3;
+ output wire [31:0] threshhold;
+ output wire [31:0] rssi_wait;
+ input wire [15:0] reg_0;
+ input wire [15:0] reg_1;
+ input wire [15:0] reg_2;
+ input wire [15:0] reg_3;
+ input wire [11:0] atr_tx_delay;
+ input wire [11:0] atr_rx_delay;
+ input wire [7:0] master_controls;
+ input wire [3:0] debug_en;
+ input wire [15:0] atr_mask_0;
+ input wire [15:0] atr_txval_0;
+ input wire [15:0] atr_rxval_0;
+ input wire [15:0] atr_mask_1;
+ input wire [15:0] atr_txval_1;
+ input wire [15:0] atr_rxval_1;
+ input wire [15:0] atr_mask_2;
+ input wire [15:0] atr_txval_2;
+ input wire [15:0] atr_rxval_2;
+ input wire [15:0] atr_mask_3;
+ input wire [15:0] atr_txval_3;
+ input wire [15:0] atr_rxval_3;
+ input wire [7:0] txa_refclk;
+ input wire [7:0] txb_refclk;
+ input wire [7:0] rxa_refclk;
+ input wire [7:0] rxb_refclk;
+ input wire [7:0] interp_rate;
+ input wire [7:0] decim_rate;
+ input wire [7:0] misc;
+ input wire [31:0] txmux;
+
+ wire [31:0] bundle[43:0];
assign bundle[0] = 32'hFFFFFFFF;
assign bundle[1] = 32'hFFFFFFFF;
assign bundle[2] = {20'd0, atr_tx_delay};
@@ -65,57 +97,57 @@
assign bundle[42] = {24'd0, txb_refclk};
assign bundle[43] = {24'd0, rxb_refclk};
- reg strobe;
- wire [31:0] out[7:0];
- assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
- assign threshhold = out[1];
- assign rssi_wait = out[2];
- assign strobe_wr = strobe;
+ reg strobe;
+ wire [31:0] out[7:0];
+ assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
+ assign threshhold = out[1];
+ assign rssi_wait = out[2];
+ assign strobe_wr = strobe;
- always @(*)
- if (reset | ~enable[1])
- begin
- strobe <= 0;
- dataout <= 0;
- end
- else
- begin
- if (enable[0])
- begin
- //read
- if (addr <= 7'd43)
- dataout <= bundle[addr];
- else if (addr <= 7'd57 && addr >= 7'd50)
- dataout <= out[addr-7'd50];
- else
- dataout <= 32'hFFFFFFFF;
- strobe <= 0;
- end
- else
- begin
- //write
- strobe <= 1;
- data_wr <= datain;
- addr_wr <= addr;
- end
- end
+ always @(*)
+ if (reset | ~enable[1])
+ begin
+ strobe <= 0;
+ dataout <= 0;
+ end
+ else
+ begin
+ if (enable[0])
+ begin
+ //read
+ if (addr <= 7'd43)
+ dataout <= bundle[addr];
+ else if (addr <= 7'd57 && addr >= 7'd50)
+ dataout <= out[addr-7'd50];
+ else
+ dataout <= 32'hFFFFFFFF;
+ strobe <= 0;
+ end
+ else
+ begin
+ //write
+ dataout <= dataout;
+ strobe <= 1;
+ data_wr <= datain;
+ addr_wr <= addr;
+ end
+ end
- //user defined registers declarations
- setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[0]));
- setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[1]));
- setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[2]));
- setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[3]));
- setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[4]));
- setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[5]));
- setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[6]));
- setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[7]));
-
-endmodule
+ //register declarations
+ setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));
+ setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
+ setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
+ setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
+ setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
+ setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5]));
+ setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
+ setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
+ .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));
+endmodule
\ No newline at end of file
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-11-14 10:32:57 UTC (rev 6895)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-11-14 15:19:32 UTC (rev 6896)
@@ -1,144 +1,179 @@
//`include "../../firmware/include/fpga_regs_common.v"
//`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer_inband
- ( //System
- input usbclk, input bus_reset, input reset, // DSP side reset (used
here), do not reset registers
+ ( input usbclk,
+ input bus_reset,
+ input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
- output [15:0] usbdata, input RD, output wire have_pkt_rdy,
- output reg rx_overrun, input wire [3:0] channels,
- input wire [15:0] ch_0, input wire [15:0] ch_1,
- input wire [15:0] ch_2, input wire [15:0] ch_3,
- input wire [15:0] ch_4, input wire [15:0] ch_5,
- input wire [15:0] ch_6, input wire [15:0] ch_7,
- input rxclk, input rxstrobe, input clear_status,
- input [6:0] serial_addr, input [31:0] serial_data,
- input serial_strobe, output wire [15:0] debugbus,
- //Connection with tx_inband
- input rx_WR, input [15:0] rx_databus,
- input rx_WR_done, output reg rx_WR_enabled,
- //signal strength
- input wire [31:0] rssi_0, input wire [31:0] rssi_1,
- input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- input wire [1:0] tx_underrun);
+ output [15:0] usbdata,
+ input RD,
+ output wire have_pkt_rdy,
+ output reg rx_overrun,
+ input wire [3:0] channels,
+ input wire [15:0] ch_0,
+ input wire [15:0] ch_1,
+ input wire [15:0] ch_2,
+ input wire [15:0] ch_3,
+ input wire [15:0] ch_4,
+ input wire [15:0] ch_5,
+ input wire [15:0] ch_6,
+ input wire [15:0] ch_7,
+ input rxclk,
+ input rxstrobe,
+ input clear_status,
+ input [6:0] serial_addr,
+ input [31:0] serial_data,
+ input serial_strobe,
+ output wire [15:0] debugbus,
+
+ //Connection with tx_inband
+ input rx_WR,
+ input [15:0] rx_databus,
+ input rx_WR_done,
+ output reg rx_WR_enabled,
+ //signal strength
+ input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+ input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+ input wire [1:0] tx_underrun
+ );
- parameter NUM_CHAN = 1;
- genvar i ;
+ parameter NUM_CHAN = 1;
+ genvar i ;
- // FX2 Bug Fix
- reg [8:0] read_count;
- always @(negedge usbclk)
- if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
- else
- read_count <= #1 RD ? read_count : 9'b0;
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
- // Time counter
- reg [31:0] adctime;
- always @(posedge rxclk)
- if (reset)
- adctime <= 0;
- else if (rxstrobe)
- adctime <= adctime + 1;
+ // Time counter
+ reg [31:0] adctime;
+ always @(posedge rxclk)
+ if (reset)
+ adctime <= 0;
+ else if (rxstrobe)
+ adctime <= adctime + 1;
- // USB side fifo
- wire [11:0] rdusedw;
- wire [11:0] wrusedw;
- wire [15:0] fifodata;
- wire WR;
- wire have_space;
+ // USB side fifo
+ wire [11:0] rdusedw;
+ wire [11:0] wrusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
- fifo_4kx16_dc rx_usb_fifo
- (.aclr (reset), .data (fifodata),
- .rdclk (~usbclk), .rdreq (RD & ~read_count[8]),
- .wrclk (rxclk), .wrreq (WR), .q (usbdata),
- .rdusedw (rdusedw), .wrusedw (wrusedw));
+ fifo_4kx16_dc rx_usb_fifo (
+ .aclr ( reset ),
+ .data ( fifodata ),
+ .rdclk ( ~usbclk ),
+ .rdreq ( RD & ~read_count[8] ),
+ .wrclk ( rxclk ),
+ .wrreq ( WR ),
+ .q ( usbdata ),
+ .rdempty ( ),
+ .rdusedw ( rdusedw ),
+ .wrfull ( ),
+ .wrusedw ( wrusedw ) );
- assign have_pkt_rdy = (rdusedw >= 12'd256);
- assign have_space = (wrusedw < 12'd760);
+ assign have_pkt_rdy = (rdusedw >= 12'd256);
+ assign have_space = (wrusedw < 12'd760);
- // Rx side fifos
- wire chan_rdreq;
- wire [15:0] chan_fifodata;
- wire [9:0] chan_usedw;
- wire [NUM_CHAN:0] chan_empty;
- wire [3:0] rd_select;
- wire [NUM_CHAN:0] rx_full;
+ // Rx side fifos
+ wire chan_rdreq;
+ wire [15:0] chan_fifodata;
+ wire [9:0] chan_usedw;
+ wire [NUM_CHAN:0] chan_empty;
+ wire [3:0] rd_select;
+ wire [NUM_CHAN:0] rx_full;
- packet_builder #(NUM_CHAN) rx_pkt_builer
- (.rxclk (rxclk), .reset (reset),
- .adctime (adctime), .channels (4'd1),
- .chan_rdreq (chan_rdreq), .chan_fifodata (chan_fifodata),
- .chan_empty (chan_empty), .rd_select (rd_select),
- .chan_usedw (chan_usedw), .WR (WR), .fifodata (fifodata),
- .have_space (have_space), .rssi_0(rssi_0), .rssi_1(rssi_1),
- .rssi_2(rssi_2), .rssi_3(rssi_3), .debugbus(debug),
.underrun(tx_underrun));
+ packet_builder #(NUM_CHAN) rx_pkt_builer (
+ .rxclk ( rxclk ),
+ .reset ( reset ),
+ .adctime ( adctime ),
+ .channels ( 4'd1 ), //need to be tested and changed to channels
+ .chan_rdreq ( chan_rdreq ),
+ .chan_fifodata ( chan_fifodata ),
+ .chan_empty ( chan_empty ),
+ .rd_select ( rd_select ),
+ .chan_usedw ( chan_usedw ),
+ .WR ( WR ),
+ .fifodata ( fifodata ),
+ .have_space ( have_space ),
+ .rssi_0(rssi_0), .rssi_1(rssi_1),
+ .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
+ .underrun(tx_underrun));
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(rx_full[0])
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
+ // Detect overrun
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rx_full[0])
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
- reg [6:0] test;
-
- always @(posedge rxclk)
- if (reset)
- test <= 0;
- else
- test <= test + 7'd1;
+ reg [6:0] test;
+ always @(posedge rxclk)
+ if (reset)
+ test <= 0;
+ else
+ test <= test + 7'd1;
- // TODO write this genericly
- wire [15:0]ch[NUM_CHAN:0];
- assign ch[0] = ch_0;
-
- wire cmd_empty;
+ // TODO write this genericly
+ wire [15:0]ch[NUM_CHAN:0];
+ assign ch[0] = ch_0;
- always @(posedge rxclk)
- if(reset)
- rx_WR_enabled <= 1;
- else if(cmd_empty)
- rx_WR_enabled <= 1;
- else if(rx_WR_done)
- rx_WR_enabled <= 0;
+ wire cmd_empty;
+ always @(posedge rxclk)
+ if(reset)
+ rx_WR_enabled <= 1;
+ else if(cmd_empty)
+ rx_WR_enabled <= 1;
+ else if(rx_WR_done)
+ rx_WR_enabled <= 0;
- wire [15:0] dataout [0:NUM_CHAN];
- wire [9:0] usedw [0:NUM_CHAN];
- wire empty [0:NUM_CHAN];
+ wire [15:0] dataout [0:NUM_CHAN];
+ wire [9:0] usedw [0:NUM_CHAN];
+ wire empty[0:NUM_CHAN];
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_fifos
-
- wire rdreq;
- assign rdreq = (rd_select == i) & chan_rdreq;
+ wire rdreq;
- fifo_1kx16 rx_chan_fifo
- (.aclr (reset), .clock (rxclk), .data (ch[i]),
- .rdreq (rdreq), .wrreq (~rx_full[i] & rxstrobe),
- .empty (empty[i]), .full (rx_full[i]), .q ( dataout[i]),
- .usedw ( usedw[i]), .almost_empty(chan_empty[i]));
+ assign rdreq = (rd_select == i) & chan_rdreq;
+ fifo_1kx16 rx_chan_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( ch[i] ),
+ .rdreq ( rdreq ),
+ .wrreq ( ~rx_full[i] & rxstrobe),
+ .empty (empty[i]),
+ .full (rx_full[i]),
+ .q ( dataout[i]),
+ .usedw ( usedw[i]),
+ .almost_empty(chan_empty[i])
+ );
end
-
- endgenerate
-
- wire [7:0] debug;
-
- fifo_1kx16 rx_cmd_fifo
- (.aclr (reset), .clock (rxclk), .data (rx_databus),
- .rdreq ((rd_select == NUM_CHAN) & chan_rdreq),
- .wrreq (rx_WR & rx_WR_enabled), .empty(cmd_empty),
- .full (rx_full[NUM_CHAN]),
- .q ( dataout[NUM_CHAN]), .usedw (usedw[NUM_CHAN]));
-
- assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
- assign chan_fifodata = dataout[rd_select];
- assign chan_usedw = usedw[rd_select];
- assign debugbus = {rxstrobe, chan_rdreq, debug,
- rx_full[0], chan_empty[0], empty[0], have_space, RD,
rxclk};
-
+ endgenerate
+ wire [7:0] debug;
+ fifo_1kx16 rx_cmd_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( rx_databus ),
+ .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
+ .wrreq ( rx_WR & rx_WR_enabled),
+ .empty ( cmd_empty),
+ .full ( rx_full[NUM_CHAN] ),
+ .q ( dataout[NUM_CHAN]),
+ .usedw ( usedw[NUM_CHAN] )
+ );
+ assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+ assign chan_fifodata = dataout[rd_select];
+ assign chan_usedw = usedw[rd_select];
+ assign debugbus = {rxstrobe, chan_rdreq, debug,
+ rx_full[0], chan_empty[0], empty[0],
have_space, RD, rxclk};
endmodule
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-11-14 10:32:57 UTC (rev 6895)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-11-14 15:19:32 UTC (rev 6896)
@@ -268,7 +268,7 @@
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
- .debugbus(tx_debugbus),
+ .debugbus(),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`else
@@ -362,8 +362,8 @@
wire [31:0] data_db;
wire strobe_db;
assign serial_strobe = strobe_db | strobe_wr;
- assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
- assign serial_data = (strobe_db)? (data_db) : (data_wr);
+ assign serial_addr = (strobe_db)? (7'd100) : (addr_wr);
+ assign serial_data = (strobe_db)? (0) : (data_wr);
//assign serial_strobe = strobe_wr;
//assign serial_data = data_wr;
//assign serial_addr = addr_wr;
@@ -388,7 +388,8 @@
wire [7:0] txa_refclk;
wire [7:0] txb_refclk;
wire [7:0] rxa_refclk;
- wire [7:0] rxb_refclk;
+ wire [7:0] rxb_refclk;
+
register_io register_control
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
.dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr),
.strobe_wr(strobe_wr),
@@ -404,6 +405,8 @@
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3),
.atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk),
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
+
+ //implementing freeze mode
reg [15:0] timestop;
wire stop;
wire [15:0] stop_time;
@@ -432,7 +435,8 @@
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1),
.atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2),
.atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3),
.atr_rxval_3(atr_rxval_3),
- .txa_refclk(txa_refclk), .txb_refclk(txb_refclk),
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
+ .txa_refclk(txa_refclk), .txb_refclk(txb_refclk),
.rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
+ .debug_0(tx_debugbus), .debug_1(rx_debugbus));
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
@@ -443,5 +447,10 @@
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc Settings
setting_reg #(`FR_MODE)
sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
-
+ reg forb;
+ assign tx_debugbus = {4'd0, forb, serial_addr, strobe_db, strobe_wr, clk64,
usbclk};
+ always @(posedge usbclk)
+ begin
+ if (strobe_db) forb <= 1;
+ end
endmodule // usrp_inband_usb
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- [Commit-gnuradio] r6896 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib toplevel/usrp_inband_usb,
zhuochen <=