[Commit-gnuradio] r6893 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-11-14 02:30:39 -0700 (Wed, 14 Nov 2007)
New Revision: 6893

Added:
   gnuradio/branches/developers/matt/u2f/control_lib/icache.v
Log:
first cut, seems to work


Added: gnuradio/branches/developers/matt/u2f/control_lib/icache.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/icache.v                  
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/icache.v  2007-11-14 
09:30:39 UTC (rev 6893)
@@ -0,0 +1,63 @@
+
+module icache
+  #(parameter AWIDTH=14,
+    parameter CWIDTH=6)
+
+    (input wb_clk_i,
+     input wb_rst_i,
+     input [AWIDTH-1:0] iwb_adr_i,
+     input iwb_stb_i,
+     output [31:0] iwb_dat_o,
+     output iwb_ack_o,
+     input [31:0] iram_dat );
+
+   localparam    TAGWIDTH = AWIDTH-CWIDTH-2;
+   reg                   stb_d1;
+   reg [AWIDTH-1:0] held_addr;
+   reg [31:0]      idata [0:(1<<CWIDTH)-1];
+   reg [TAGWIDTH-1:0] itags [0:(1<<CWIDTH)-1];
+   reg                       ivalid [0:(1<<CWIDTH)-1];
+
+   // //////////////////////////////////////
+   // Handle 1-cycle delay of Block-RAM
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       stb_d1 <= 0;
+     else
+       stb_d1 <= iwb_stb_i;
+   
+   always @(posedge wb_clk_i)
+     if(~wb_rst_i)
+       held_addr <= iwb_adr_i;
+
+   // /////////////////////////////////////
+   // Load from the cache
+   integer           i;
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       for(i=0;i<(1<<CWIDTH);i=i+1)
+        ivalid[i] <= 0;
+     else
+       if(stb_d1)
+        ivalid[held_addr[CWIDTH+1:2]] <= 1'b1;
+   
+   always @(posedge wb_clk_i)
+     if(stb_d1)
+       begin
+         idata[held_addr[CWIDTH+1:2]] <= iram_dat;
+         itags[held_addr[CWIDTH+1:2]] <= held_addr[AWIDTH-1:CWIDTH+2];
+       end
+   
+   // //////////////////////////////////////
+   // Read from Cache
+   wire [CWIDTH-1:0] line = iwb_adr_i[CWIDTH+1:2];
+   wire [31:0]              cdata_out = idata[line];
+   wire [TAGWIDTH-1:0] tag_out = itags[line];
+   wire               valid_out = ivalid[line];
+   
+   // //////////////////////////////////////
+   // Very basic, no forwarding
+   assign             iwb_dat_o = idata[line];
+   assign             iwb_ack_o = ivalid[line] & 
+                      (tag_out == iwb_adr_i[AWIDTH-1:CWIDTH+2]);
+endmodule // icache