[Commit-gnuradio] r6885 - gnuradio/branches/developers/matt/u2f/top/u2_basic

[matt]

Author: matt
Date: 2007-11-13 14:09:44 -0700 (Tue, 13 Nov 2007)
New Revision: 6885

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
added in uart


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-11-13 21:09:17 UTC (rev 6884)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-11-13 21:09:44 UTC (rev 6885)
@@ -114,6 +114,11 @@
    // GPIO to DBoards
    inout [15:0] io_tx,
    inout [15:0] io_rx,
+
+   // Debug stuff
+   output uart_tx_o, 
+   input uart_rx_i,
+   output uart_baud_o,
    input sim_mode
    );
    
@@ -127,10 +132,11 @@
    wire [31:0]         ser_debug;
 
    wire [31:0]         status, status_b0, status_b1, status_b2, status_b3, 
status_b4, status_b5, status_b6, status_b7;
-   wire        bus_error, spi_int, i2c_int, timer_int, buffer_int, proc_int, 
overrun, underrun;
+   wire        bus_error, spi_int, i2c_int, timer_int, buffer_int, proc_int, 
overrun, underrun, uart_int;
 
-   wire [31:0]         debug_wb;
+   wire [31:0]         debug_wb, debug_txmacfifo_in, debug_txmacfifo_out;
    wire [15:0]         debug_gmii_1, debug_gmii_2;
+
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
@@ -140,20 +146,20 @@
    wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
    wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, 
s2_dat_i, s3_dat_i,
                 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, 
s6_dat_i, s7_dat_i,
-                s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i;
-   wire [aw-1:0] m0_adr, m1_adr, 
s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr;
-   wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, 
s5_sel, s6_sel, s7_sel, s8_sel, s9_sel;
-   wire         m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, 
s5_ack, s6_ack, s7_ack, s8_ack, s9_ack;
-   wire         m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, 
s5_stb, s6_stb, s7_stb, s8_stb, s9_stb;
-   wire         m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, 
s5_cyc, s6_cyc, s7_cyc, s8_cyc, s9_cyc;
-   wire         m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, 
s5_err, s6_err, s7_err, s8_err, s9_err;
-   wire         m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, 
s5_rty, s6_rty, s7_rty, s8_rty, s9_rty;
-   wire         m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, 
s7_we, s8_we, s9_we;
+                s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i;
+   wire [aw-1:0] m0_adr, m1_adr, 
s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr;
+   wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, 
s5_sel, s6_sel, s7_sel, s8_sel, s9_sel, s10_sel;
+   wire         m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, 
s5_ack, s6_ack, s7_ack, s8_ack, s9_ack, s10_ack;
+   wire         m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, 
s5_stb, s6_stb, s7_stb, s8_stb, s9_stb, s10_stb;
+   wire         m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, 
s5_cyc, s6_cyc, s7_cyc, s8_cyc, s9_cyc, s10_cyc;
+   wire         m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, 
s5_err, s6_err, s7_err, s8_err, s9_err, s10_err;
+   wire         m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, 
s5_rty, s6_rty, s7_rty, s8_rty, s9_rty, s10_rty;
+   wire         m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, 
s7_we, s8_we, s9_we, s10_we;
    
    wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01),
                
.s215_addr_w(5),.s2_addr(5'b10000),.s3_addr(5'b10010),.s4_addr(5'b10100),
                
.s5_addr(5'b10110),.s6_addr(5'b11000),.s7_addr(5'b11010),.s8_addr(5'b11100),.s9_addr(5'b11101),
-               
.s10_addr(5'b11111),.s11_addr(5'b11111),.s12_addr(5'b11111),.s13_addr(5'b11111),
+               
.s10_addr(5'b11110),.s11_addr(5'b11111),.s12_addr(5'b11111),.s13_addr(5'b11111),
                .s14_addr(5'b11111),.s15_addr(5'b11111),
                .dw(dw),.aw(aw),.sw(sw)) wb_1master
      (.clk_i(wb_clk),.rst_i(wb_rst),       
@@ -179,7 +185,8 @@
       
.s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty),
       .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o 
(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
       
.s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty),
-      .s10_dat_i(0),.s10_ack_i(0),.s10_err_i(0),.s10_rty_i(0),
+      
.s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb),
+      
.s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty),
       .s11_dat_i(0),.s11_ack_i(0),.s11_err_i(0),.s11_rty_i(0),
       .s12_dat_i(0),.s12_ack_i(0),.s12_err_i(0),.s12_rty_i(0),
       .s13_dat_i(0),.s13_ack_i(0),.s13_err_i(0),.s13_rty_i(0),
@@ -322,7 +329,7 @@
    nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
                 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
                 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
-                .debug_0( {debug_wb[15:0],debug_wb[31:16]} 
),.debug_1({debug_gmii_2,debug_gmii_1}),
+                .debug_0( debug_txmacfifo_in 
),.debug_1({debug_gmii_2,debug_gmii_1}),
                 .gpio( {io_tx,io_rx} ) );
    assign       s4_err = 1'b0;
    assign       s4_rty = 1'b0;
@@ -425,8 +432,10 @@
    simple_pic simple_pic
      
(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
       
.we_i(s8_we),.dat_i(s8_dat_o[7:0]),.dat_o(s8_dat_i[7:0]),.ack_o(s8_ack),.int_o(proc_int),
-      
.irq({1'b0,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}) );
+      
.irq({uart_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}) 
);
    assign       s8_dat_i[31:8] = 0;
+   assign       s8_err = 0;
+   assign       s8_rty = 0;
         
    // /////////////////////////////////////////////////////////////////////////
    // Master Timer, Slave #9
@@ -437,8 +446,27 @@
       .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[2:0]),
       .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
       .sys_clk_i(dsp_clk),.master_time_o(master_time),.int_o(timer_int) );
+   assign       s9_err = 0;
+   assign       s9_rty = 0;
    
+   assign       exp_pps_out = 1'b0;
+
    // /////////////////////////////////////////////////////////////////////////
+   // UART, Slave #10
+
+   uart_top uart
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+      .wb_adr_i(s10_adr[4:0]),.wb_dat_i(s10_dat_o),.wb_dat_o(s10_dat_i),
+      
.wb_we_i(s10_we),.wb_stb_i(s10_stb),.wb_cyc_i(s10_cyc),.wb_ack_o(s10_ack),
+      .wb_sel_i(s10_sel),.int_o(uart_int),
+      .stx_pad_o(uart_tx_o),.srx_pad_i(uart_rx_i),
+      
.rts_pad_o(),.cts_pad_i(1'b0),.dtr_pad_o(),.dsr_pad_i(1'b0),.ri_pad_i(1'b0),.dcd_pad_i(1'b0),
+      .baud_o(uart_baud_o) );
+
+   assign       s10_err = 0;
+   assign       s10_rty = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
    // DSP
 
    reg [13:0]   adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
@@ -532,9 +560,12 @@
 
    assign      debug_gmii_1 = {GMII_GTX_CLK,GMII_TX_CLK,debug_gmii_1_reg};
    assign      debug_gmii_2 = {GMII_RX_CLK,1'b0,debug_gmii_2_reg};
+
+   assign      debug_txmacfifo_out = {Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, 
Tx_mac_eop, 1'b0, Tx_mac_data[26:0]};
+   assign      debug_txmacfifo_in = {rd2_read, rd2_done, rd2_sop, rd2_eop, 
rd2_error, rd2_dat[26:0]};
+
+   assign      debug = debug_txmacfifo_out;
    
-   assign      debug = debug_new;
-   
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk;