[Commit-gnuradio] r6877 - gnuradio/branches/developers/matt/u2f/models

[matt]

Author: matt
Date: 2007-11-13 01:17:34 -0700 (Tue, 13 Nov 2007)
New Revision: 6877

Added:
   gnuradio/branches/developers/matt/u2f/models/BUFG.v
   gnuradio/branches/developers/matt/u2f/models/uart_rx.v
Log:
first cut at a uart printout function


Added: gnuradio/branches/developers/matt/u2f/models/BUFG.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/models/BUFG.v                         
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/models/BUFG.v 2007-11-13 08:17:34 UTC 
(rev 6877)
@@ -0,0 +1,33 @@
+// $Header: 
/devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5 
2005/03/14 22:32:51 yanx Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 8.1i (I.13)
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Global Clock Buffer
+// /___/   /\     Filename : BUFG.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:42:14 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+// End Revision
+
+`timescale  100 ps / 10 ps
+
+
+module BUFG (O, I);
+
+    output O;
+
+    input  I;
+
+       buf B1 (O, I);
+
+
+endmodule
+

Added: gnuradio/branches/developers/matt/u2f/models/uart_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/models/uart_rx.v                      
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/models/uart_rx.v      2007-11-13 
08:17:34 UTC (rev 6877)
@@ -0,0 +1,44 @@
+
+
+// Simple printout of characters from the UART
+//   Only does 8N1, requires the baud clock
+
+module uart_rx (input baudclk, input rxd);
+   reg [10:0] sr = 11'b0;
+   reg [3:0]  baud_ctr = 4'b0;
+   wire       byteclk = baud_ctr[3];
+
+   reg               rxd_d1 = 0;
+   always @(posedge baudclk)
+     rxd_d1 <= rxd;
+   
+   always @(posedge baudclk)
+     if(rxd_d1 != rxd)
+       baud_ctr <= 0;
+     else
+       baud_ctr <= baud_ctr + 1;
+
+   always @(posedge byteclk)
+     sr <= { sr[9:0], rxd };
+
+   reg [3:0]  state = 0;
+   always @(posedge byteclk)
+     case(state)
+       0 : 
+        if(~sr[1] & sr[0])  // found start bit
+          state  <= 1;
+       1, 2, 3, 4, 5, 6, 7, 8 :
+        state <= state + 1;
+       9 : 
+        begin
+           state <= 0;
+           if(sr[0])
+             $display("Error, no stop bit\n");
+           $write("%c",sr[8:1]);
+        end
+       default :
+        state <= 0;
+     endcase // case(state)
+   
+endmodule // uart_rx
+