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[Commit-gnuradio] r6865 - in gnuradio/branches/developers/matt/u2f/openc
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From: |
matt |
|
Subject: |
[Commit-gnuradio] r6865 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sim sim/CVS sim/verilog sim/verilog/CVS sw sw/CVS sw/c sw/c/CVS |
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Date: |
Sun, 11 Nov 2007 14:08:50 -0700 (MST) |
Author: matt
Date: 2007-11-11 14:08:48 -0700 (Sun, 11 Nov 2007)
New Revision: 6865
Removed:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bsft.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_mult.v
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regf.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/iversim
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/edk32.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
Log:
latest and greatest from Shawn as of 11/11/07. Now does mul,div,mfs, etc.
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-11-11 20:01:06 UTC (rev 6864)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,18 +1,16 @@
/aeMB_ucore.v/1.1/Fri Apr 13 13:02:34 2007//
/aeMB_wbbus.v/1.1/Tue May 8 20:32:13 2007//
-/aeMB_bpcu.v/1.2/Fri Nov 2 19:20:58 2007//
-/aeMB_bsft.v/1.2/Sat Nov 3 08:34:54 2007//
-/aeMB_ctrl.v/1.2/Fri Nov 2 19:20:58 2007//
-/aeMB_edk32.v/1.3/Sat Nov 3 08:34:55 2007//
-/aeMB_ibuf.v/1.3/Sat Nov 3 08:34:55 2007//
-/aeMB_mult.v/1.2/Sat Nov 3 08:34:55 2007//
-/aeMB_regf.v/1.1/Fri Nov 2 03:25:41 2007//
-/aeMB_scon.v/1.2/Fri Nov 2 19:20:58 2007//
-/aeMB_xecu.v/1.3/Sat Nov 3 08:34:55 2007//
/aeMB_aslu.v/1.11/Sat Nov 3 19:53:43 2007//
/aeMB_control.v/1.8/Sat Nov 3 19:53:44 2007//
/aeMB_core.v/1.8/Sat Nov 3 19:53:44 2007//
/aeMB_decode.v/1.11/Sat Nov 3 19:53:44 2007//
/aeMB_fetch.v/1.7/Sat Nov 3 19:53:44 2007//
/aeMB_regfile.v/1.19/Sat Nov 3 19:53:44 2007//
+/aeMB_bpcu.v/1.3/Sun Nov 11 19:45:40 2007//
+/aeMB_ctrl.v/1.6/Sun Nov 11 19:45:41 2007//
+/aeMB_edk32.v/1.7/Sun Nov 11 19:45:41 2007//
+/aeMB_ibuf.v/1.4/Sun Nov 11 19:45:41 2007//
+/aeMB_regf.v/1.3/Sun Nov 11 19:45:41 2007//
+/aeMB_scon.v/1.5/Sun Nov 11 19:45:41 2007//
+/aeMB_xecu.v/1.6/Sun Nov 11 19:45:41 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
2007-11-11 20:01:06 UTC (rev 6864)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,25 +1,29 @@
-// $Id: aeMB_bpcu.v,v 1.2 2007/11/02 19:20:58 sybreon Exp $
+// $Id: aeMB_bpcu.v,v 1.3 2007/11/10 16:39:38 sybreon Exp $
//
// AEMB BRANCH PROGRAMME COUNTER UNIT
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
//
-// This library is free software; you can redistribute it and/or
-// modify it under the terms of the GNU Lesser General Public License
-// as published by the Free Software Foundation; either version 2.1 of
-// the License, or (at your option) any later version.
+// This file is part of AEMB.
//
-// This library is distributed in the hope that it will be useful, but
-// WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-// Lesser General Public License for more details.
-//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+// Public License for more details.
+//
// You should have received a copy of the GNU Lesser General Public
-// License along with this library; if not, write to the Free Software
-// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-// USA
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_bpcu.v,v $
+// Revision 1.3 2007/11/10 16:39:38 sybreon
+// Upgraded license to LGPLv3.
+// Significant performance optimisations.
+//
// Revision 1.2 2007/11/02 19:20:58 sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
Deleted:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bsft.v
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
2007-11-11 20:01:06 UTC (rev 6864)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
2007-11-11 21:08:48 UTC (rev 6865)
@@ -28,31 +28,37 @@
input sys_exc_i);
assign dwb_cyc_o = dwb_stb_o;
- /*
+
+`define NEW_AEMB 1
+`ifdef NEW_AEMB
aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ))
- aeMB_core (.sys_clk_i(sys_clk_i),
- .sys_rst_i(sys_rst_i),
-
- .iwb_stb_o(iwb_stb_o),
- .iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
- .iwb_ack_i(iwb_ack_i),
- .iwb_dat_i(iwb_dat_i),
-
- .dwb_wre_o(dwb_we_o),
- .dwb_stb_o(dwb_stb_o),
- .dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
- .dwb_ack_i(dwb_ack_i),
- .dwb_sel_o(dwb_sel_o),
- .dwb_dat_i(dwb_dat_i),
- .dwb_dat_o(dwb_dat_o),
-
- .sys_int_i(sys_int_i) );
-
+ aeMB_edk32 (.sys_clk_i(~sys_clk_i),
+ .sys_rst_i(sys_rst_i),
+
+ .iwb_stb_o(iwb_stb_o),
+ .iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
+ .iwb_ack_i(iwb_ack_i),
+ .iwb_dat_i(iwb_dat_i),
+
+ .dwb_wre_o(dwb_we_o),
+ .dwb_stb_o(dwb_stb_o),
+ .dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
+ .dwb_ack_i(dwb_ack_i),
+ .dwb_sel_o(dwb_sel_o),
+ .dwb_dat_i(dwb_dat_i),
+ .dwb_dat_o(dwb_dat_o),
+
+ .fsl_wre_o(),
+ .fsl_stb_o(),
+ .fsl_dat_o(),
+ .fsl_adr_o(),
+ .fsl_dat_i(32'b0),
+ .fsl_ack_i(1'b0),
+ .sys_int_i(sys_int_i) );
+
assign iwb_adr_o[1:0] = 2'b0;
assign dwb_adr_o[1:0] = 2'b0;
- */
-
-
+`else
aeMB_core #(.ISIZ(ISIZ),.DSIZ(DSIZ))
aeMB_core (.sys_clk_i(sys_clk_i),
.sys_rst_i(~sys_rst_i),
@@ -71,5 +77,5 @@
.dwb_dat_o(dwb_dat_o),
.sys_int_i(sys_int_i) );
-
+`endif
endmodule // aeMB_core_BE
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
2007-11-11 20:01:06 UTC (rev 6864)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,25 +1,38 @@
-// $Id: aeMB_ctrl.v,v 1.2 2007/11/02 19:20:58 sybreon Exp $
+// $Id: aeMB_ctrl.v,v 1.6 2007/11/10 16:39:38 sybreon Exp $
//
// AEMB CONTROL UNIT
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
//
-// This library is free software; you can redistribute it and/or
-// modify it under the terms of the GNU Lesser General Public License
-// as published by the Free Software Foundation; either version 2.1 of
-// the License, or (at your option) any later version.
+// This file is part of AEMB.
//
-// This library is distributed in the hope that it will be useful, but
-// WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-// Lesser General Public License for more details.
-//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+// Public License for more details.
+//
// You should have received a copy of the GNU Lesser General Public
-// License along with this library; if not, write to the Free Software
-// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-// USA
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_ctrl.v,v $
+// Revision 1.6 2007/11/10 16:39:38 sybreon
+// Upgraded license to LGPLv3.
+// Significant performance optimisations.
+//
+// Revision 1.5 2007/11/09 20:51:52 sybreon
+// Added GET/PUT support through a FSL bus.
+//
+// Revision 1.4 2007/11/08 17:48:14 sybreon
+// Fixed data WISHBONE arbitration problem (reported by J Lee).
+//
+// Revision 1.3 2007/11/08 14:17:47 sybreon
+// Parameterised optional components.
+//
// Revision 1.2 2007/11/02 19:20:58 sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
@@ -32,11 +45,11 @@
module aeMB_ctrl (/*AUTOARG*/
// Outputs
- rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, dwb_stb_o,
- dwb_wre_o,
+ rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, rFSLSTB,
+ dwb_stb_o, dwb_wre_o, fsl_stb_o, fsl_wre_o,
// Inputs
rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
- gclk, grst, gena
+ dwb_ack_i, iwb_ack_i, iwb_dat_i, fsl_ack_i, gclk, grst, gena
);
// INTERNAL
//output [31:2] rPCLNK;
@@ -44,7 +57,9 @@
output [1:0] rMXSRC, rMXTGT, rMXALT;
output [2:0] rMXALU;
output [4:0] rRW;
- output rDWBSTB;
+ output rDWBSTB;
+ output rFSLSTB;
+
input [1:0] rXCE;
input rDLY;
input [15:0] rIMM;
@@ -58,13 +73,29 @@
// DATA WISHBONE
output dwb_stb_o;
output dwb_wre_o;
+ input dwb_ack_i;
+
+ // INST WISHBONE
+ input iwb_ack_i;
+ input [31:0] iwb_dat_i;
+ // FSL WISHBONE
+ output fsl_stb_o;
+ output fsl_wre_o;
+ input fsl_ack_i;
+
// SYSTEM
input gclk, grst, gena;
// --- DECODE INSTRUCTIONS
// TODO: Simplify
+ wire [5:0] wOPC;
+ wire [4:0] wRD, wRA, wRB;
+ wire [10:0] wALT;
+
+ assign {wOPC, wRD, wRA, wRB, wALT} = iwb_dat_i; // FIXME: Endian
+
wire fSFT = (rOPC == 6'o44);
wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
@@ -84,9 +115,47 @@
wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
wire fLDST = (&rOPC[5:4]);
+ wire fPUT = (rOPC == 6'o33) & rRB[4];
+ wire fGET = (rOPC == 6'o33) & !rRB[4];
+
+
+ wire wSFT = (wOPC == 6'o44);
+ wire wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);
+
+ wire wMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
+ wire wBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
+ wire wDIV = (wOPC == 6'o22);
+ wire wRTD = (wOPC == 6'o55);
+ wire wBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
+ wire wBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
+ wire wBRA = wBRU & wRA[3];
+
+ wire wIMM = (wOPC == 6'o54);
+ wire wMOV = (wOPC == 6'o45);
+
+ wire wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
+ wire wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
+ wire wLDST = (&wOPC[5:4]);
+
+ wire wPUT = (wOPC == 6'o33) & wRB[4];
+ wire wGET = (wOPC == 6'o33) & !wRB[4];
+
+
+ // --- BRANCH SLOT REGISTERS ---------------------------
+
+ reg [31:2] rPCLNK, xPCLNK;
+ reg [1:0] rMXDST, xMXDST;
+ reg [4:0] rRW, xRW;
+
+ reg [1:0] rMXSRC, xMXSRC;
+ reg [1:0] rMXTGT, xMXTGT;
+ reg [1:0] rMXALT, xMXALT;
+
+
// --- OPERAND SELECTOR ---------------------------------
+ /*
wire fRDWE = |rRW;
wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
wire fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;
@@ -106,13 +175,43 @@
assign rMXALT = (fAFWD_M) ? 2'o2 : // RAM
(fAFWD_R) ? 2'o1 : // FWD
2'o0; // REG
+ */
+
+ wire wRDWE = |xRW;
+ wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
+ wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
+ wire wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;
+ wire wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
+
+ always @(/*AUTOSENSE*/rBRA or rXCE or wAFWD_M or wAFWD_R or wBCC
+ or wBFWD_M or wBFWD_R or wBRU or wOPC)
+ if (rBRA | |rXCE) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xMXALT <= 2'h0;
+ xMXSRC <= 2'h0;
+ xMXTGT <= 2'h0;
+ // End of automatics
+ end else begin
+ xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC
+ (wAFWD_M) ? 2'o2 : // RAM
+ (wAFWD_R) ? 2'o1 : // FWD
+ 2'o0; // REG
+ xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM
+ (wBFWD_M) ? 2'o2 : // RAM
+ (wBFWD_R) ? 2'o1 : // FWD
+ 2'o0; // REG
+ xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
+ (wAFWD_R) ? 2'o1 : // FWD
+ 2'o0; // REG
+ end
-
// --- ALU CONTROL ---------------------------------------
+ /*
reg [2:0] rMXALU;
- always @(/*AUTOSENSE*/fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
- or fSFT) begin
+ always @(fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
+ or fSFT) begin
rMXALU <= (fBRA | fMOV) ? 3'o3 :
(fSFT) ? 3'o2 :
(fLOG) ? 3'o1 :
@@ -121,38 +220,33 @@
(fDIV) ? 3'o6 :
3'o0;
end
-
-
- // --- RAM CONTROL ---------------------------------------
+ */
- reg rDWBSTB, xDWBSTB;
- reg rDWBWRE, xDWBWRE;
+ reg [2:0] rMXALU, xMXALU;
- assign dwb_stb_o = rDWBSTB;
- assign dwb_wre_o = rDWBWRE;
-
- // --- DELAY SLOT REGISTERS ------------------------------
-
- reg [31:2] rPCLNK, xPCLNK;
- reg [1:0] rMXDST, xMXDST;
- reg [4:0] rRW, xRW;
-
- wire fSKIP = (rBRA & !rDLY);
-
- always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or rXCE)
- if (fSKIP | |rXCE) begin
+ always @(/*AUTOSENSE*/rBRA or rXCE or wBRA or wBSF or wDIV or wLOG
+ or wMOV or wMUL or wSFT)
+ if (rBRA | |rXCE) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
- xDWBSTB <= 1'h0;
- xDWBWRE <= 1'h0;
+ xMXALU <= 3'h0;
// End of automatics
end else begin
- xDWBSTB <= fLOD | fSTR;
- xDWBWRE <= fSTR;
+ xMXALU <= (wBRA | wMOV) ? 3'o3 :
+ (wSFT) ? 3'o2 :
+ (wLOG) ? 3'o1 :
+ (wMUL) ? 3'o4 :
+ (wBSF) ? 3'o5 :
+ (wDIV) ? 3'o6 :
+ 3'o0;
end
- always @(/*AUTOSENSE*/fBCC or fBRU or fLOD or fRTD or fSKIP or fSTR
- or rRD or rXCE)
+ // --- DELAY SLOT REGISTERS ------------------------------
+
+ wire fSKIP = (rBRA & !rDLY);
+
+ always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
+ or fSTR or rRD or rXCE)
if (fSKIP) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
@@ -163,7 +257,7 @@
case (rXCE)
2'o2: xMXDST <= 2'o1;
default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
- (fLOD) ? 2'o2 :
+ (fLOD | fGET) ? 2'o2 :
(fBRU) ? 2'o1 :
2'o0;
endcase
@@ -174,26 +268,100 @@
endcase
end // else: !if(fSKIP)
+
+
+ // --- DATA WISHBONE ----------------------------------
+
+ wire fDACK = !(rDWBSTB ^ dwb_ack_i);
+ reg rDWBSTB, xDWBSTB;
+ reg rDWBWRE, xDWBWRE;
+
+ assign dwb_stb_o = rDWBSTB;
+ assign dwb_wre_o = rDWBWRE;
+
+ always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i or rXCE)
+ if (fSKIP | |rXCE) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xDWBSTB <= 1'h0;
+ xDWBWRE <= 1'h0;
+ // End of automatics
+ end else begin
+ xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
+ xDWBWRE <= fSTR & iwb_ack_i;
+ end
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rDWBSTB <= 1'h0;
+ rDWBWRE <= 1'h0;
+ // End of automatics
+ end else if (fDACK) begin
+ rDWBSTB <= #1 xDWBSTB;
+ rDWBWRE <= #1 xDWBWRE;
+ end
+
+
+ // --- FSL WISHBONE -----------------------------------
+
+ wire fFACK = !(rFSLSTB ^ fsl_ack_i);
+
+ reg rFSLSTB, xFSLSTB;
+ reg rFSLWRE, xFSLWRE;
+
+ assign fsl_stb_o = rFSLSTB;
+ assign fsl_wre_o = rFSLWRE;
+
+ always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i or rXCE)
+ if (fSKIP | |rXCE) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xFSLSTB <= 1'h0;
+ xFSLWRE <= 1'h0;
+ // End of automatics
+ end else begin
+ xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
+ xFSLWRE <= fPUT & iwb_ack_i;
+ end
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rFSLSTB <= 1'h0;
+ rFSLWRE <= 1'h0;
+ // End of automatics
+ end else if (fFACK) begin
+ rFSLSTB <= #1 xFSLSTB;
+ rFSLWRE <= #1 xFSLWRE;
+ end
+
// --- PIPELINE CONTROL DELAY ----------------------------
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
- rDWBSTB <= 1'h0;
- rDWBWRE <= 1'h0;
+ rMXALT <= 2'h0;
+ rMXALU <= 3'h0;
rMXDST <= 2'h0;
+ rMXSRC <= 2'h0;
+ rMXTGT <= 2'h0;
rRW <= 5'h0;
// End of automatics
end else if (gena) begin
//rPCLNK <= #1 xPCLNK;
rMXDST <= #1 xMXDST;
rRW <= #1 xRW;
- rDWBSTB <= #1 xDWBSTB;
- rDWBWRE <= #1 xDWBWRE;
+ rMXSRC <= #1 xMXSRC;
+ rMXTGT <= #1 xMXTGT;
+ rMXALT <= #1 xMXALT;
+ rMXALU <= #1 xMXALU;
end
+
-
endmodule // aeMB_ctrl
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
2007-11-11 20:01:06 UTC (rev 6864)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,25 +1,38 @@
-// $Id: aeMB_edk32.v,v 1.3 2007/11/03 08:34:55 sybreon Exp $
+// $Id: aeMB_edk32.v,v 1.7 2007/11/10 16:39:38 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
//
-// This library is free software; you can redistribute it and/or
-// modify it under the terms of the GNU Lesser General Public License
-// as published by the Free Software Foundation; either version 2.1 of
-// the License, or (at your option) any later version.
+// This file is part of AEMB.
//
-// This library is distributed in the hope that it will be useful, but
-// WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-// Lesser General Public License for more details.
-//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+// Public License for more details.
+//
// You should have received a copy of the GNU Lesser General Public
-// License along with this library; if not, write to the Free Software
-// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-// USA
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_edk32.v,v $
+// Revision 1.7 2007/11/10 16:39:38 sybreon
+// Upgraded license to LGPLv3.
+// Significant performance optimisations.
+//
+// Revision 1.6 2007/11/09 20:51:52 sybreon
+// Added GET/PUT support through a FSL bus.
+//
+// Revision 1.5 2007/11/08 17:48:14 sybreon
+// Fixed data WISHBONE arbitration problem (reported by J Lee).
+//
+// Revision 1.4 2007/11/08 14:17:47 sybreon
+// Parameterised optional components.
+//
// Revision 1.3 2007/11/03 08:34:55 sybreon
// Minor code cleanup.
//
@@ -35,15 +48,19 @@
module aeMB_edk32 (/*AUTOARG*/
// Outputs
- iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
- dwb_adr_o,
+ iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_stb_o, fsl_dat_o, fsl_adr_o,
+ dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
// Inputs
- sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
- dwb_ack_i
+ sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
+ fsl_ack_i, dwb_dat_i, dwb_ack_i
);
+ // Bus widths
+ parameter IW = 32; /// Instruction bus address width
+ parameter DW = 32; /// Data bus address width
- parameter IW = 32;
- parameter DW = 32;
+ // Optional functions
+ parameter MUL = 1; // Multiplier
+ parameter BSF = 1; // Barrel Shifter
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
@@ -52,15 +69,21 @@
output [3:0] dwb_sel_o; // From xecu of
aeMB_xecu.v
output dwb_stb_o; // From ctrl of aeMB_ctrl.v
output dwb_wre_o; // From ctrl of aeMB_ctrl.v
+ output [14:2] fsl_adr_o; // From xecu of aeMB_xecu.v
+ output [31:0] fsl_dat_o; // From regf of aeMB_regf.v
+ output fsl_stb_o; // From ctrl of aeMB_ctrl.v
+ output fsl_wre_o; // From ctrl of aeMB_ctrl.v
output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
output iwb_stb_o; // From ibuf of aeMB_ibuf.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
- input dwb_ack_i; // To scon of aeMB_scon.v
+ input dwb_ack_i; // To scon of aeMB_scon.v, ...
input [31:0] dwb_dat_i; // To regf of
aeMB_regf.v
+ input fsl_ack_i; // To scon of aeMB_scon.v, ...
+ input [31:0] fsl_dat_i; // To regf of
aeMB_regf.v
input iwb_ack_i; // To scon of aeMB_scon.v, ...
- input [31:0] iwb_dat_i; // To ibuf of
aeMB_ibuf.v
+ input [31:0] iwb_dat_i; // To ibuf of
aeMB_ibuf.v, ...
input sys_clk_i; // To scon of aeMB_scon.v
input sys_int_i; // To scon of aeMB_scon.v
input sys_rst_i; // To scon of aeMB_scon.v
@@ -77,6 +100,7 @@
wire [31:0] rDWBDI; // From regf of aeMB_regf.v
wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v
wire rDWBSTB; // From ctrl of
aeMB_ctrl.v
+ wire rFSLSTB; // From ctrl of
aeMB_ctrl.v
wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v
wire rMSR_BIP; // From xecu of
aeMB_xecu.v
wire rMSR_IE; // From xecu of
aeMB_xecu.v
@@ -98,34 +122,7 @@
wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
wire [1:0] rXCE; // From scon of aeMB_scon.v
// End of automatics
-
- wire [31:0] rOPA, rOPB;
- wire [31:0] rRES_MUL, rRES_BSF;
-
- // --- OPTIONAL COMPONENTS -----------------------------------
- // Trade off hardware size/speed for software speed
-
- aeMB_mult
- mult (
- // Outputs
- .rRES_MUL (rRES_MUL[31:0]),
- // Inputs
- .rOPA (rOPA[31:0]),
- .rOPB (rOPB[31:0]));
-
- aeMB_bsft
- bsft (
- // Outputs
- .rRES_BSF (rRES_BSF[31:0]),
- // Inputs
- .rOPA (rOPA[31:0]),
- .rOPB (rOPB[31:0]),
- .rALT (rALT[10:0]));
-
-
- // --- NON-OPTIONAL COMPONENTS -------------------------------
- // These components make up the main AEMB processor.
-
+
aeMB_scon
scon (/*AUTOINST*/
// Outputs
@@ -137,8 +134,10 @@
.rOPC (rOPC[5:0]),
.rATOM (rATOM[1:0]),
.rDWBSTB (rDWBSTB),
+ .rFSLSTB (rFSLSTB),
.dwb_ack_i (dwb_ack_i),
.iwb_ack_i (iwb_ack_i),
+ .fsl_ack_i (fsl_ack_i),
.rMSR_IE (rMSR_IE),
.rMSR_BIP (rMSR_BIP),
.rBRA (rBRA),
@@ -177,8 +176,11 @@
.rMXALU (rMXALU[2:0]),
.rRW (rRW[4:0]),
.rDWBSTB (rDWBSTB),
+ .rFSLSTB (rFSLSTB),
.dwb_stb_o (dwb_stb_o),
.dwb_wre_o (dwb_wre_o),
+ .fsl_stb_o (fsl_stb_o),
+ .fsl_wre_o (fsl_wre_o),
// Inputs
.rXCE (rXCE[1:0]),
.rDLY (rDLY),
@@ -191,6 +193,10 @@
.rPC (rPC[31:2]),
.rBRA (rBRA),
.rMSR_IE (rMSR_IE),
+ .dwb_ack_i (dwb_ack_i),
+ .iwb_ack_i (iwb_ack_i),
+ .iwb_dat_i (iwb_dat_i[31:0]),
+ .fsl_ack_i (fsl_ack_i),
.gclk (gclk),
.grst (grst),
.gena (gena));
@@ -224,6 +230,7 @@
.rREGB (rREGB[31:0]),
.rDWBDI (rDWBDI[31:0]),
.dwb_dat_o (dwb_dat_o[31:0]),
+ .fsl_dat_o (fsl_dat_o[31:0]),
// Inputs
.rOPC (rOPC[5:0]),
.rRA (rRA[4:0]),
@@ -237,18 +244,17 @@
.rBRA (rBRA),
.rDLY (rDLY),
.dwb_dat_i (dwb_dat_i[31:0]),
+ .fsl_dat_i (fsl_dat_i[31:0]),
.gclk (gclk),
.grst (grst),
.gena (gena));
- aeMB_xecu #(DW)
- xecu (
- .rOPA (rOPA[31:0]),
- .rOPB (rOPB[31:0]),
- /*AUTOINST*/
+ aeMB_xecu #(DW, MUL, BSF)
+ xecu (/*AUTOINST*/
// Outputs
.dwb_adr_o (dwb_adr_o[DW-1:2]),
.dwb_sel_o (dwb_sel_o[3:0]),
+ .fsl_adr_o (fsl_adr_o[14:2]),
.rRESULT (rRESULT[31:0]),
.rDWBSEL (rDWBSEL[3:0]),
.rMSR_IE (rMSR_IE),
@@ -260,17 +266,17 @@
.rMXSRC (rMXSRC[1:0]),
.rMXTGT (rMXTGT[1:0]),
.rRA (rRA[4:0]),
+ .rRB (rRB[4:0]),
.rMXALU (rMXALU[2:0]),
.rBRA (rBRA),
.rDLY (rDLY),
+ .rALT (rALT[10:0]),
.rSIMM (rSIMM[31:0]),
.rIMM (rIMM[15:0]),
.rOPC (rOPC[5:0]),
.rRD (rRD[4:0]),
.rDWBDI (rDWBDI[31:0]),
.rPC (rPC[31:2]),
- .rRES_MUL (rRES_MUL[31:0]),
- .rRES_BSF (rRES_BSF[31:0]),
.gclk (gclk),
.grst (grst),
.gena (gena));
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
2007-11-11 20:01:06 UTC (rev 6864)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,25 +1,29 @@
-// $Id: aeMB_ibuf.v,v 1.3 2007/11/03 08:34:55 sybreon Exp $
+// $Id: aeMB_ibuf.v,v 1.4 2007/11/10 16:39:38 sybreon Exp $
//
// AEMB INSTRUCTION BUFFER
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
//
-// This library is free software; you can redistribute it and/or
-// modify it under the terms of the GNU Lesser General Public License
-// as published by the Free Software Foundation; either version 2.1 of
-// the License, or (at your option) any later version.
+// This file is part of AEMB.
//
-// This library is distributed in the hope that it will be useful, but
-// WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-// Lesser General Public License for more details.
-//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+// Public License for more details.
+//
// You should have received a copy of the GNU Lesser General Public
-// License along with this library; if not, write to the Free Software
-// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-// USA
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_ibuf.v,v $
+// Revision 1.4 2007/11/10 16:39:38 sybreon
+// Upgraded license to LGPLv3.
+// Significant performance optimisations.
+//
// Revision 1.3 2007/11/03 08:34:55 sybreon
// Minor code cleanup.
//
Deleted:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_mult.v
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regf.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regf.v
2007-11-11 20:01:06 UTC (rev 6864)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regf.v
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,25 +1,32 @@
-// $Id: aeMB_regf.v,v 1.1 2007/11/02 03:25:41 sybreon Exp $
+// $Id: aeMB_regf.v,v 1.3 2007/11/10 16:39:38 sybreon Exp $
//
// AEMB REGISTER FILE
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
//
-// This library is free software; you can redistribute it and/or
-// modify it under the terms of the GNU Lesser General Public License
-// as published by the Free Software Foundation; either version 2.1 of
-// the License, or (at your option) any later version.
+// This file is part of AEMB.
//
-// This library is distributed in the hope that it will be useful, but
-// WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-// Lesser General Public License for more details.
-//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+// Public License for more details.
+//
// You should have received a copy of the GNU Lesser General Public
-// License along with this library; if not, write to the Free Software
-// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-// USA
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_regf.v,v $
+// Revision 1.3 2007/11/10 16:39:38 sybreon
+// Upgraded license to LGPLv3.
+// Significant performance optimisations.
+//
+// Revision 1.2 2007/11/09 20:51:52 sybreon
+// Added GET/PUT support through a FSL bus.
+//
// Revision 1.1 2007/11/02 03:25:41 sybreon
// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
// Fixed various minor data hazard bugs.
@@ -28,10 +35,10 @@
module aeMB_regf (/*AUTOARG*/
// Outputs
- rREGA, rREGB, rDWBDI, dwb_dat_o,
+ rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o,
// Inputs
rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
- rDLY, dwb_dat_i, gclk, grst, gena
+ rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena
);
// INTERNAL
output [31:0] rREGA, rREGB;
@@ -47,6 +54,10 @@
// DATA WISHBONE
output [31:0] dwb_dat_o;
input [31:0] dwb_dat_i;
+
+ // FSL WISHBONE
+ output [31:0] fsl_dat_o;
+ input [31:0] fsl_dat_i;
// SYSTEM
input gclk, grst, gena;
@@ -55,24 +66,81 @@
// Moves the data bytes around depending on the size of the
// operation.
- wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
+ wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
+ wire [31:0] wFSLDI = fsl_dat_i; // FIXME: Endian
+
reg [31:0] rDWBDI;
+ reg [1:0] rSIZ;
- always @(/*AUTOSENSE*/rDWBSEL or wDWBDI)
- case (rDWBSEL)
- // 8'bit
- 4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
- 4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
- 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
- 4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]};
- // 16'bit
- 4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
- 4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
- // 32'bit
- 4'hF: rDWBDI <= wDWBDI;
- // Undefined
- default: rDWBDI <= 32'hX;
- endcase
+ always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin
+ /* 51.2
+ case (rSIZ)
+ // FSL
+ 2'o3: rDWBDI <= wFSLDI;
+ // 32'bit
+ 2'o2: rDWBDI <= wDWBDI;
+ // 16'bit
+ 2'o1: case (rRESULT[1])
+ 1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]};
+ 1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]};
+ endcase // case (rRESULT[1])
+ // 8'bit
+ 2'o0: case (rRESULT[1:0])
+ 2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]};
+ 2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]};
+ 2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]};
+ 2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]};
+ endcase // case (rRESULT[1:0])
+ endcase // case (rSIZ)
+ */
+
+ /* 50.6
+ case ({rSIZ, rRESULT[1:0]})
+ // FSL
+ 4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI;
+ // 32'bit
+ 4'h8: rDWBDI <= wDWBDI;
+ // 16'bit
+ 4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]};
+ 4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]};
+ // 8'bit
+ 4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]};
+ 4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]};
+ 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
+ 4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]};
+ default: rDWBDI <= 32'hX;
+ endcase // case (rSIZ)
+ */
+
+ // 52.0
+ case (rDWBSEL)
+ // 8'bit
+ 4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
+ 4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
+ 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
+ 4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]};
+ // 16'bit
+ 4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
+ 4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
+ // 32'bit
+ 4'hF: rDWBDI <= wDWBDI;
+ // FSL
+ 4'h0: rDWBDI <= wFSLDI;
+ // Undefined
+ default: rDWBDI <= 32'hX;
+ endcase
+
+ end
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rSIZ <= 2'h0;
+ // End of automatics
+ end else if (gena) begin
+ rSIZ <= rOPC[1:0];
+ end
// --- GENERAL PURPOSE REGISTERS (R0-R31) -----------------------
// LUT RAM implementation is smaller and faster. R0 gets written
@@ -111,17 +179,27 @@
// Replicates the data bytes across depending on the size of the
// operation.
+ reg [31:0] rDWBDO, xDWBDO;
+
+ wire [31:0] xFSL;
+ wire fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE;
+ wire fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE;
+
+ assign fsl_dat_o = rDWBDO;
+ assign xFSL = (fFFWD_M) ? rDWBDI :
+ (fFFWD_R) ? rRESULT :
+ rREGA;
+
wire [31:0] xDST;
wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;
- reg [31:0] rDWBDO, xDWBDO;
assign dwb_dat_o = rDWBDO;
assign xDST = (fDFWD_M) ? rDWBDI :
(fDFWD_R) ? rRESULT :
rREGD;
- always @(/*AUTOSENSE*/rOPC or xDST)
+ always @(/*AUTOSENSE*/rOPC or xDST or xFSL)
case (rOPC[1:0])
// 8'bit
2'h0: xDWBDO <= {(4){xDST[7:0]}};
@@ -129,7 +207,9 @@
2'h1: xDWBDO <= {(2){xDST[15:0]}};
// 32'bit
2'h2: xDWBDO <= xDST;
- default: xDWBDO <= 32'hX;
+ // FSL
+ 2'h3: xDWBDO <= xFSL;
+ //default: xDWBDO <= 32'hX;
endcase // case (rOPC[1:0])
always @(posedge gclk)
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
2007-11-11 20:01:06 UTC (rev 6864)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,25 +1,35 @@
-// $Id: aeMB_scon.v,v 1.2 2007/11/02 19:20:58 sybreon Exp $
+// $Id: aeMB_scon.v,v 1.5 2007/11/10 16:39:38 sybreon Exp $
//
// AEMB SYSTEM CONTROL UNIT
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
//
-// This library is free software; you can redistribute it and/or
-// modify it under the terms of the GNU Lesser General Public License
-// as published by the Free Software Foundation; either version 2.1 of
-// the License, or (at your option) any later version.
+// This file is part of AEMB.
//
-// This library is distributed in the hope that it will be useful, but
-// WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-// Lesser General Public License for more details.
-//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+// Public License for more details.
+//
// You should have received a copy of the GNU Lesser General Public
-// License along with this library; if not, write to the Free Software
-// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-// USA
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_scon.v,v $
+// Revision 1.5 2007/11/10 16:39:38 sybreon
+// Upgraded license to LGPLv3.
+// Significant performance optimisations.
+//
+// Revision 1.4 2007/11/09 20:51:52 sybreon
+// Added GET/PUT support through a FSL bus.
+//
+// Revision 1.3 2007/11/04 05:24:59 sybreon
+// Fixed spurious interrupt latching during long bus cycles (spotted by J Lee).
+//
// Revision 1.2 2007/11/02 19:20:58 sybreon
// Added better (beta) interrupt support.
// Changed MSR_IE to disabled at reset as per MB docs.
@@ -34,8 +44,8 @@
// Outputs
rXCE, grst, gclk, gena,
// Inputs
- rOPC, rATOM, rDWBSTB, dwb_ack_i, iwb_ack_i, rMSR_IE, rMSR_BIP,
- rBRA, rDLY, sys_clk_i, sys_rst_i, sys_int_i
+ rOPC, rATOM, rDWBSTB, rFSLSTB, dwb_ack_i, iwb_ack_i, fsl_ack_i,
+ rMSR_IE, rMSR_BIP, rBRA, rDLY, sys_clk_i, sys_rst_i, sys_int_i
);
// INTERNAL
@@ -44,8 +54,11 @@
input [1:0] rATOM;
input rDWBSTB;
+ input rFSLSTB;
input dwb_ack_i;
- input iwb_ack_i;
+ input iwb_ack_i;
+ input fsl_ack_i;
+
input rMSR_IE;
input rMSR_BIP;
@@ -56,51 +69,55 @@
input sys_clk_i, sys_rst_i;
input sys_int_i;
-
assign gclk = sys_clk_i;
- assign gena = !((rDWBSTB ^ dwb_ack_i) | !iwb_ack_i);
+ assign gena = !((rDWBSTB ^ dwb_ack_i) | (rFSLSTB ^ fsl_ack_i) |
!iwb_ack_i);
- // --- INTERRUPT LATCH ---------------------------------
-
+ // --- INTERRUPT LATCH --------------------------------------
+ // Debounce and latch onto the positive edge. This is independent
+ // of the pipeline so that stalls do not affect it.
+
reg rFINT;
reg [1:0] rDINT;
- wire wSHOT = rDINT[0] & !rDINT[1] & sys_int_i; // +Edge
+ wire wSHOT = rDINT[0] & !rDINT[1] & sys_int_i;
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDINT <= 2'h0;
+ rFINT <= 1'h0;
// End of automatics
end else if (rMSR_IE) begin
rDINT <= #1 {rDINT[0], sys_int_i};
+ rFINT <= (rXCE == 2'o2) ? 1'b0 : (rFINT | wSHOT);
end
+
+ // --- EXCEPTION PROCESSING ---------------------------------
+ // Process the independent priority flags to determine which
+ // interrupt/exception/break to handle.
+
+ reg [1:0] rXCE;
+ reg rENA;
+ wire fINT = rENA & ^rATOM & !rMSR_BIP & rMSR_IE & rFINT;
+
+ always @(/*AUTOSENSE*/fINT)
+ rXCE <= (fINT) ? 2'o2 : 2'o0;
+
always @(posedge gclk)
if (grst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
- rFINT <= 1'h0;
+ rENA <= 1'h0;
// End of automatics
- end else if (gena) begin
- rFINT <= (rXCE == 2'o2) ? 1'b0 : (rFINT | wSHOT);
+ end else begin
+ rENA <= #1 gena;
end
-
- // --- EXCEPTION PROCESSING ----------------------------
-
- reg [1:0] rXCE;
-
- always @(/*AUTOSENSE*/rATOM or rFINT or rMSR_BIP or rMSR_IE)
- case (rATOM)
- default: rXCE <= (!rMSR_BIP & rMSR_IE & rFINT) ? 2'o2 :
- 2'o0;
- 2'o0, 2'o3: rXCE <= 0;
- endcase // case (rATOM)
+ // --- RESET SYNCHRONISER -----------------------------------
+ // Synchronise the reset signal to a clock edge.
- // --- RESET SYNCHRONISER ------------------------------
-
reg [1:0] rRST;
assign grst = sys_rst_i;
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
2007-11-11 20:01:06 UTC (rev 6864)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,25 +1,35 @@
-// $Id: aeMB_xecu.v,v 1.3 2007/11/03 08:34:55 sybreon Exp $
+// $Id: aeMB_xecu.v,v 1.6 2007/11/10 16:39:38 sybreon Exp $
//
// AEMB MAIN EXECUTION ALU
//
// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
//
-// This library is free software; you can redistribute it and/or
-// modify it under the terms of the GNU Lesser General Public License
-// as published by the Free Software Foundation; either version 2.1 of
-// the License, or (at your option) any later version.
+// This file is part of AEMB.
//
-// This library is distributed in the hope that it will be useful, but
-// WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-// Lesser General Public License for more details.
-//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+// Public License for more details.
+//
// You should have received a copy of the GNU Lesser General Public
-// License along with this library; if not, write to the Free Software
-// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
-// USA
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_xecu.v,v $
+// Revision 1.6 2007/11/10 16:39:38 sybreon
+// Upgraded license to LGPLv3.
+// Significant performance optimisations.
+//
+// Revision 1.5 2007/11/09 20:51:52 sybreon
+// Added GET/PUT support through a FSL bus.
+//
+// Revision 1.4 2007/11/08 14:17:47 sybreon
+// Parameterised optional components.
+//
// Revision 1.3 2007/11/03 08:34:55 sybreon
// Minor code cleanup.
//
@@ -35,40 +45,45 @@
module aeMB_xecu (/*AUTOARG*/
// Outputs
- dwb_adr_o, dwb_sel_o, rRESULT, rOPA, rOPB, rDWBSEL, rMSR_IE,
+ dwb_adr_o, dwb_sel_o, fsl_adr_o, rRESULT, rDWBSEL, rMSR_IE,
rMSR_BIP,
// Inputs
- rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rMXALU, rBRA, rDLY, rSIMM,
- rIMM, rOPC, rRD, rDWBDI, rPC, rRES_MUL, rRES_BSF, gclk, grst, gena
+ rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY,
+ rALT, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
);
parameter DW=32;
+
+ parameter MUL=0;
+ parameter BSF=0;
// DATA WISHBONE
output [DW-1:2] dwb_adr_o;
output [3:0] dwb_sel_o;
+
+ // FSL WISHBONE
+ output [14:2] fsl_adr_o;
// INTERNAL
output [31:0] rRESULT;
- output [31:0] rOPA, rOPB;
output [3:0] rDWBSEL;
output rMSR_IE;
output rMSR_BIP;
input [1:0] rXCE;
input [31:0] rREGA, rREGB;
input [1:0] rMXSRC, rMXTGT;
- input [4:0] rRA;
+ input [4:0] rRA, rRB;
input [2:0] rMXALU;
input rBRA, rDLY;
+ input [10:0] rALT;
- //input [1:0] rXCE;
input [31:0] rSIMM;
input [15:0] rIMM;
input [5:0] rOPC;
input [4:0] rRD;
input [31:0] rDWBDI;
input [31:2] rPC;
- input [31:0] rRES_MUL; // External Multiplier
- input [31:0] rRES_BSF; // External Barrel Shifter
+ //input [31:0] rRES_MUL; // External Multiplier
+ //input [31:0] rRES_BSF; // External Barrel Shifter
// SYSTEM
input gclk, grst, gena;
@@ -100,6 +115,7 @@
endcase // case (rMXTGT)
// --- ADD/SUB SELECTOR ----
+ // FIXME: Redesign
// TODO: Refactor
// TODO: Verify signed compare
@@ -127,7 +143,7 @@
default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
- // --- LOGIC SELECTOR ---
+ // --- LOGIC SELECTOR --------------------------------------
reg [31:0] rRES_LOG;
always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
@@ -138,7 +154,7 @@
2'o3: rRES_LOG <= #1 rOPA & ~rOPB;
endcase // case (rOPC[1:0])
- // --- SHIFT SELECTOR ---
+ // --- SHIFTER SELECTOR ------------------------------------
reg [31:0] rRES_SFT;
reg rRES_SFTC;
@@ -152,7 +168,7 @@
{ {(24){rOPA[7]}}, rOPA[7:0], rMSR_C};
endcase // case (rIMM[6:5])
- // --- MOVE SELECTOR ---
+ // --- MOVE SELECTOR ---------------------------------------
wire [31:0] wMSR = {rMSR_C, 3'o0,
20'h0ED32,
@@ -167,7 +183,72 @@
(rRA[3]) ? rOPB :
rOPA;
+ // --- MULTIPLIER ------------------------------------------
+
+ reg [31:0] rRES_MUL;
+ always @(/*AUTOSENSE*/rOPA or rOPB) begin
+ rRES_MUL <= (rOPA * rOPB);
+ end
+
+ // --- BARREL SHIFTER --------------------------------------
+
+ reg [31:0] rRES_BSF;
+ reg [31:0] xBSRL, xBSRA, xBSLL;
+ // Infer a logical left barrel shifter.
+ always @(/*AUTOSENSE*/rOPA or rOPB)
+ xBSLL <= rOPA << rOPB[4:0];
+
+ // Infer a logical right barrel shifter.
+ always @(/*AUTOSENSE*/rOPA or rOPB)
+ xBSRL <= rOPA >> rOPB[4:0];
+
+ // Infer a arithmetic right barrel shifter.
+ always @(/*AUTOSENSE*/rOPA or rOPB)
+ case (rOPB[4:0])
+ 5'd00: xBSRA <= rOPA;
+ 5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};
+ 5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};
+ 5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]};
+ 5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]};
+ 5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]};
+ 5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]};
+ 5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]};
+ 5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]};
+ 5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]};
+ 5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]};
+ 5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]};
+ 5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]};
+ 5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]};
+ 5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]};
+ 5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]};
+ 5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]};
+ 5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]};
+ 5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]};
+ 5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]};
+ 5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]};
+ 5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]};
+ 5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]};
+ 5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]};
+ 5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]};
+ 5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]};
+ 5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]};
+ 5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]};
+ 5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]};
+ 5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};
+ 5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};
+ 5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
+ endcase // case (rOPB[4:0])
+
+ always @(/*AUTOSENSE*/rALT or xBSLL or xBSRA or xBSRL)
+ case (rALT[10:9])
+ 2'd0: rRES_BSF <= xBSRL;
+ 2'd1: rRES_BSF <= xBSRA;
+ 2'd2: rRES_BSF <= xBSLL;
+ default: rRES_BSF <= 32'hX;
+ endcase // case (rALT[10:9])
+
+
// --- MSR REGISTER -----------------
// C
@@ -209,8 +290,8 @@
always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA)
xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE;
- // --- RESULT SELECTOR
-
+ // --- RESULT SELECTOR -------------------------------------------
+ // Selects results from functional units.
reg [31:0] rRESULT, xRESULT;
// RESULT
@@ -227,8 +308,8 @@
3'o1: xRESULT <= rRES_LOG;
3'o2: xRESULT <= rRES_SFT;
3'o3: xRESULT <= rRES_MOV;
- 3'o4: xRESULT <= rRES_MUL;
- 3'o5: xRESULT <= rRES_BSF;
+ 3'o4: xRESULT <= (MUL) ? rRES_MUL : 32'hX;
+ 3'o5: xRESULT <= (BSF) ? rRES_BSF : 32'hX;
default: xRESULT <= 32'hX;
endcase // case (rMXALU)
@@ -240,17 +321,27 @@
always @(/*AUTOSENSE*/rOPC or wADD)
case (rOPC[1:0])
- 2'o0: case (wADD[1:0])
+ 2'o0: case (wADD[1:0]) // 8'bit
2'o0: xDWBSEL <= 4'h8;
2'o1: xDWBSEL <= 4'h4;
2'o2: xDWBSEL <= 4'h2;
2'o3: xDWBSEL <= 4'h1;
endcase // case (wADD[1:0])
- 2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC;
- 2'o2: xDWBSEL <= 4'hF;
- default: xDWBSEL <= 4'hX;
+ 2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC; // 16'bit
+ 2'o2: xDWBSEL <= 4'hF; // 32'bit
+ 2'o3: xDWBSEL <= 4'h0; // FSL
endcase // case (rOPC[1:0])
+
+ // --- FSL WISHBONE --------------------
+
+ reg [14:2] rFSLADR, xFSLADR;
+ assign fsl_adr_o = rFSLADR[14:2];
+
+ always @(/*AUTOSENSE*/rALT or rRB) begin
+ xFSLADR <= {rALT, rRB[3:2]};
+ end
+
// --- SYNC ---
always @(posedge gclk)
@@ -258,6 +349,7 @@
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBSEL <= 4'h0;
+ rFSLADR <= 13'h0;
rMSR_BE <= 1'h0;
rMSR_BIP <= 1'h0;
rMSR_C <= 1'h0;
@@ -270,7 +362,8 @@
rMSR_C <= #1 xMSR_C;
rMSR_IE <= #1 xMSR_IE;
rMSR_BE <= #1 xMSR_BE;
- rMSR_BIP <= #1 xMSR_BIP;
+ rMSR_BIP <= #1 xMSR_BIP;
+ rFSLADR <= #1 xFSLADR;
end
endmodule // aeMB_xecu
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries
2007-11-11 20:01:06 UTC (rev 6864)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,3 +1,3 @@
-/iversim/1.1/Fri Mar 9 17:41:55 2007//
-/cversim/1.2/Sat Apr 14 06:52:57 2007//
D/verilog////
+/cversim/1.3/Sun Nov 11 19:45:41 2007//
+/iversim/1.3/Sun Nov 11 19:45:41 2007//
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
2007-11-11 20:01:06 UTC (rev 6864)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,6 +1,9 @@
#!/bin/sh
-# $Id: cversim,v 1.2 2007/04/12 20:21:33 sybreon Exp $
+# $Id: cversim,v 1.3 2007/11/05 10:59:31 sybreon Exp $
# $Log: cversim,v $
+# Revision 1.3 2007/11/05 10:59:31 sybreon
+# Added random seed for simulation.
+#
# Revision 1.2 2007/04/12 20:21:33 sybreon
# Moved testbench into /sim/verilog.
# Simulation cleanups.
@@ -8,4 +11,6 @@
# Revision 1.1 2007/03/09 17:41:55 sybreon
# initial import
#
+RANDOM=$(date +%s)
+echo "parameter randseed = $RANDOM;" > random.v
cver -q -w $@ ../rtl/verilog/*.v
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/iversim
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/iversim
2007-11-11 20:01:06 UTC (rev 6864)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/iversim
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,7 +1,15 @@
#!/bin/sh
-# $Id: iversim,v 1.1 2007/03/09 17:41:55 sybreon Exp $
+# $Id: iversim,v 1.3 2007/11/09 20:50:51 sybreon Exp $
# $Log: iversim,v $
+# Revision 1.3 2007/11/09 20:50:51 sybreon
+# Added log output to iverilog.log
+#
+# Revision 1.2 2007/11/05 10:59:31 sybreon
+# Added random seed for simulation.
+#
# Revision 1.1 2007/03/09 17:41:55 sybreon
# initial import
#
-iverilog $@ ../rtl/verilog/*.v && vvp a.out && rm a.out
+RANDOM=$(date +%s)
+echo "parameter randseed = $RANDOM;" > random.v
+iverilog $@ ../rtl/verilog/*.v && vvp -l iverilog.log a.out && rm a.out
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
2007-11-11 20:01:06 UTC (rev 6864)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,4 +1,4 @@
/utestbench.v/1.1/Fri Apr 13 13:02:34 2007//
-/edk32.v/1.2/Fri Nov 2 19:16:10 2007//
/testbench.v/1.6/Sat Nov 3 19:53:44 2007//
+/edk32.v/1.5/Sun Nov 11 19:45:41 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/edk32.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/edk32.v
2007-11-11 20:01:06 UTC (rev 6864)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/edk32.v
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,4 +1,4 @@
-// $Id: edk32.v,v 1.2 2007/11/02 19:16:10 sybreon Exp $
+// $Id: edk32.v,v 1.5 2007/11/09 20:51:53 sybreon Exp $
//
// AEMB EDK 3.2 Compatible Core TEST
//
@@ -20,6 +20,15 @@
// USA
//
// $Log: edk32.v,v $
+// Revision 1.5 2007/11/09 20:51:53 sybreon
+// Added GET/PUT support through a FSL bus.
+//
+// Revision 1.4 2007/11/08 14:18:00 sybreon
+// Parameterised optional components.
+//
+// Revision 1.3 2007/11/05 10:59:31 sybreon
+// Added random seed for simulation.
+//
// Revision 1.2 2007/11/02 19:16:10 sybreon
// Added interrupt simulation.
// Changed "human readable" simulation output.
@@ -31,24 +40,27 @@
//
module edk32 ();
-
-
+
+`include "random.v"
+
// INITIAL SETUP //////////////////////////////////////////////////////
reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
reg svc;
integer inttime;
+ integer seed;
always #5 sys_clk_i = ~sys_clk_i;
initial begin
- //$dumpfile("dump.vcd");
- //$dumpvars(1,dut);
+ $dumpfile("dump.vcd");
+ $dumpvars(1,dut);
end
initial begin
+ seed = randseed;
svc = 0;
- sys_clk_i = 1;
+ sys_clk_i = $random(seed);
sys_rst_i = 1;
sys_int_i = 0;
sys_exc_i = 0;
@@ -65,13 +77,19 @@
// FAKE MEMORY ////////////////////////////////////////////////////////
+
+ wire [14:2] fsl_adr_o;
+ wire fsl_stb_o;
+ wire fsl_wre_o;
+ wire [31:0] fsl_dat_o;
+ wire [31:0] fsl_dat_i;
wire [15:2] iwb_adr_o;
wire iwb_stb_o;
wire dwb_stb_o;
reg [31:0] rom [0:65535];
wire [31:0] iwb_dat_i;
- reg iwb_ack_i, dwb_ack_i;
+ reg iwb_ack_i, dwb_ack_i, fsl_ack_i;
reg [31:0] ram[0:65535];
wire [31:0] dwb_dat_i;
@@ -86,10 +104,14 @@
assign
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
assign
{iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
assign {dwb_dat_t} = ram[dwb_adr_o];
+
+ assign fsl_dat_i = fsl_adr_o;
always @(negedge sys_clk_i) begin
iwb_ack_i <= #1 iwb_stb_o;
dwb_ack_i <= #1 dwb_stb_o;
+ fsl_ack_i <= #1 fsl_stb_o;
+
iadr <= #1 iwb_adr_o;
dadr <= dwb_adr_o;
@@ -209,7 +231,17 @@
2'o2: $write("BSLLI");
default: $write("XXX");
endcase // case (dut.rALT[10:9])
- 6'o33: $write("GETPUT");
+ 6'o33: case (dut.rRB[4:2])
+ 3'o0: $write("GET");
+ 3'o4: $write("PUT");
+ 3'o2: $write("NGET");
+ 3'o6: $write("NPUT");
+ 3'o1: $write("CGET");
+ 3'o5: $write("CPUT");
+ 3'o3: $write("NCGET");
+ 3'o7: $write("NCPUT");
+ endcase // case (dut.rRB[4:2])
+
6'o40: $write("OR");
6'o41: $write("AND");
@@ -293,8 +325,8 @@
// ALU
$write("\t");
//$writeh(" I=",dut.rSIMM);
- $writeh(" A=",dut.rOPA);
- $writeh(" B=",dut.rOPB);
+ $writeh(" A=",dut.xecu.rOPA);
+ $writeh(" B=",dut.xecu.rOPB);
case (dut.rMXALU)
3'o0: $write(" ADD");
@@ -312,7 +344,10 @@
if (dut.regf.fRDWE) begin
case (dut.rMXDST)
- 2'o2: $writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");
+ 2'o2: begin
+ if (dut.dwb_stb_o)
$writeh("R",dut.rRW,"=RAM(h",dut.regf.xWDAT,")");
+ if (dut.fsl_stb_o)
$writeh("R",dut.rRW,"=FSL(h",dut.regf.xWDAT,")");
+ end
2'o1: $writeh("R",dut.rRW,"=LNK(h",dut.regf.xWDAT,")");
2'o0: $writeh("R",dut.rRW,"=ALU(h",dut.regf.xWDAT,")");
endcase // case (dut.rMXDST)
@@ -336,6 +371,14 @@
.dwb_dat_i(dwb_dat_i),
.dwb_wre_o(dwb_we_o),
.dwb_sel_o(dwb_sel_o),
+
+ .fsl_ack_i(fsl_ack_i),
+ .fsl_stb_o(fsl_stb_o),
+ .fsl_adr_o(fsl_adr_o),
+ .fsl_dat_o(fsl_dat_o),
+ .fsl_dat_i(fsl_dat_i),
+ .fsl_wre_o(fsl_we_o),
+
.iwb_adr_o(iwb_adr_o),
.iwb_dat_i(iwb_dat_i),
.iwb_stb_o(iwb_stb_o),
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
2007-11-11 20:01:06 UTC (rev 6864)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,2 +1,2 @@
D/c////
-/gccrom/1.6/Sat Nov 3 19:53:44 2007//
+/gccrom/1.8/Sun Nov 11 19:47:07 2007//
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
2007-11-11 20:01:06 UTC (rev 6864)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,2 +1,2 @@
-/aeMB_testbench.c/1.8/Sat Nov 3 19:53:44 2007//
+/aeMB_testbench.c/1.9/Sun Nov 11 19:45:41 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
2007-11-11 20:01:06 UTC (rev 6864)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_testbench.c,v 1.8 2007/11/03 08:40:18 sybreon Exp $
+ * $Id: aeMB_testbench.c,v 1.9 2007/11/09 20:51:53 sybreon Exp $
*
* AEMB Function Verification C Testbench
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_testbench.c,v $
+ * Revision 1.9 2007/11/09 20:51:53 sybreon
+ * Added GET/PUT support through a FSL bus.
+ *
* Revision 1.8 2007/11/03 08:40:18 sybreon
* Minor code cleanup.
*
@@ -267,7 +270,30 @@
return 0;
}
+
/**
+ FSL TEST ROUTINE
+*/
+
+int fsl_test ()
+{
+ // TEST FSL1 ONLY
+ int FSL = 0xCAFEF00D;
+
+ asm ("PUT %0, RFSL1" :: "r"(FSL));
+ asm ("GET %0, RFSL1" : "=r"(FSL));
+
+ if (FSL != 0x04) return -1;
+
+ asm ("PUT %0, RFSL31" :: "r"(FSL));
+ asm ("GET %0, RFSL31" : "=r"(FSL));
+
+ if (FSL != 0x7C) return -1;
+
+ return 0;
+}
+
+/**
MAIN TEST PROGRAMME
This is the main test procedure. It will output signals onto the
@@ -283,6 +309,9 @@
// Number of each test to run
int max = 10;
+ // FSL TEST
+ if (fsl_test() == -1) { *mpi = 0x4641494C; }
+
// Enable Global Interrupts
int_enable();
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
2007-11-11 20:01:06 UTC (rev 6864)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
2007-11-11 21:08:48 UTC (rev 6865)
@@ -1,6 +1,12 @@
#!/bin/sh
-# $Id: gccrom,v 1.6 2007/11/02 03:25:46 sybreon Exp $
+# $Id: gccrom,v 1.8 2007/11/09 20:52:37 sybreon Exp $
# $Log: gccrom,v $
+# Revision 1.8 2007/11/09 20:52:37 sybreon
+# Added some compilation optimisations.
+#
+# Revision 1.7 2007/11/04 05:16:25 sybreon
+# Added -msoft-float and -mxl-soft-div compiler flags.
+#
# Revision 1.6 2007/11/02 03:25:46 sybreon
# New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
# Fixed various minor data hazard bugs.
@@ -22,7 +28,7 @@
# initial import
#
#mb-gcc -g -mxl-soft-div -mxl-soft-mul -msoft-float -mno-clearbss
-msmall-divides -mno-memcpy -mno-xl-gp-opt -o rom.o $@ && \
-mb-gcc -g -mstats -mxl-soft-div -mxl-soft-float -o rom.o $@ && \
+mb-gcc -g -mstats -mxl-soft-div -msoft-float -mno-memcpy -msmall-divides -o
rom.o $@ && \
#mb-run -v rom.o 2> rom.run && \
mb-objcopy -O binary rom.o rom.bin && \
hexdump -v -e'1/4 "%.8X\n"' rom.bin > ../sim/aeMB.rom && \
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