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[Commit-gnuradio] r6810 - gnuradio/branches/developers/matt/u2f/opencore
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From: |
matt |
|
Subject: |
[Commit-gnuradio] r6810 - gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog |
|
Date: |
Sun, 4 Nov 2007 17:37:45 -0700 (MST) |
Author: matt
Date: 2007-11-04 17:37:45 -0700 (Sun, 04 Nov 2007)
New Revision: 6810
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bsft.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_mult.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regf.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
Log:
new version of the aemb core, includes barrel shift and multiplier. Not tried
yet.
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bpcu.v
2007-11-05 00:37:45 UTC (rev 6810)
@@ -0,0 +1,173 @@
+// $Id: aeMB_bpcu.v,v 1.2 2007/11/02 19:20:58 sybreon Exp $
+//
+// AEMB BRANCH PROGRAMME COUNTER UNIT
+//
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public License
+// as published by the Free Software Foundation; either version 2.1 of
+// the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//
+// $Log: aeMB_bpcu.v,v $
+// Revision 1.2 2007/11/02 19:20:58 sybreon
+// Added better (beta) interrupt support.
+// Changed MSR_IE to disabled at reset as per MB docs.
+//
+// Revision 1.1 2007/11/02 03:25:39 sybreon
+// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+// Fixed various minor data hazard bugs.
+// Code compatible with -O0/1/2/3/s generated code.
+//
+
+module aeMB_bpcu (/*AUTOARG*/
+ // Outputs
+ iwb_adr_o, rPC, rPCLNK, rBRA, rDLY, rATOM,
+ // Inputs
+ rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, rXCE, gclk, grst,
+ gena
+ );
+ parameter IW = 24;
+
+ // INST WISHBONE
+ output [IW-1:2] iwb_adr_o;
+
+ // INTERNAL
+ output [31:2] rPC, rPCLNK;
+ output rBRA;
+ output rDLY;
+ output [1:0] rATOM;
+ input [1:0] rMXALT;
+ input [5:0] rOPC;
+ input [4:0] rRD, rRA;
+ input [31:0] rRESULT; // ALU
+ input [31:0] rDWBDI; // RAM
+ input [31:0] rREGA;
+ input [1:0] rXCE;
+
+ // SYSTEM
+ input gclk, grst, gena;
+
+ // --- BRANCH CONTROL --------------------------------------------
+ // Controls the branch and delay flags
+
+ wire fRTD = (rOPC == 6'o55);
+ wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
+ wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
+
+ wire [31:0] wREGA;
+ assign wREGA = (rMXALT == 2'o2) ? rDWBDI :
+ (rMXALT == 2'o1) ? rRESULT :
+ rREGA;
+
+ wire wBEQ = (wREGA == 32'd0);
+ wire wBNE = ~wBEQ;
+ wire wBLT = wREGA[31];
+ wire wBLE = wBLT | wBEQ;
+ wire wBGE = ~wBLT;
+ wire wBGT = ~wBLE;
+
+ reg xXCC;
+ always @(/*AUTOSENSE*/rRD or wBEQ or wBGE or wBGT or wBLE or wBLT
+ or wBNE)
+ case (rRD[2:0])
+ 3'o0: xXCC <= wBEQ;
+ 3'o1: xXCC <= wBNE;
+ 3'o2: xXCC <= wBLT;
+ 3'o3: xXCC <= wBLE;
+ 3'o4: xXCC <= wBGT;
+ 3'o5: xXCC <= wBGE;
+ default: xXCC <= 1'bX;
+ endcase // case (rRD[2:0])
+
+ reg rBRA, xBRA;
+ reg rDLY, xDLY;
+ wire fSKIP = rBRA & !rDLY;
+
+ always @(/*AUTOSENSE*/fBCC or fBRU or fRTD or rBRA or rRA or rRD
+ or rXCE or xXCC)
+ if (rBRA | |rXCE) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xBRA <= 1'h0;
+ xDLY <= 1'h0;
+ // End of automatics
+ end else begin
+ xDLY <= (fBRU & rRA[4]) | (fBCC & rRD[4]) | fRTD;
+ xBRA <= (fRTD | fBRU) ? 1'b1 :
+ (fBCC) ? xXCC :
+ 1'b0;
+ end
+
+ // --- PC PIPELINE ------------------------------------------------
+ // PC and related changes
+
+ reg [31:2] rIPC, xIPC;
+ reg [31:2] rPC, xPC;
+ reg [31:2] rPCLNK, xPCLNK;
+
+ assign iwb_adr_o = rIPC[IW-1:2];
+
+ always @(/*AUTOSENSE*/rATOM or rBRA or rIPC or rPC or rRESULT
+ or rXCE) begin
+ xPCLNK <= (^rATOM) ? rPC : rPC;
+ //xPCLNK <= rPC;
+ //xPC <= (^rATOM) ? rIPC : rRESULT[31:2];
+ xPC <= rIPC;
+ //xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
+ case (rXCE)
+ 2'o1: xIPC <= 30'h2;
+ 2'o2: xIPC <= 30'h4;
+ 2'o3: xIPC <= 30'h6;
+ default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
+ endcase // case (rXCE)
+ end
+
+ // --- ATOMIC CONTROL ---------------------------------------------
+ // This is used to indicate 'safe' instruction borders.
+
+ wire wIMM = (rOPC == 6'o54) & !fSKIP;
+ wire wRTD = (rOPC == 6'o55) & !fSKIP;
+ wire wBCC = xXCC & ((rOPC == 6'o47) | (rOPC == 6'o57)) & !fSKIP;
+ wire wBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)) & !fSKIP;
+
+ wire fATOM = ~(wIMM | wRTD | wBCC | wBRU | rBRA);
+ reg [1:0] rATOM, xATOM;
+
+ always @(/*AUTOSENSE*/fATOM or rATOM)
+ xATOM <= {rATOM[0], (rATOM[0] ^ fATOM)};
+
+
+ // --- SYNC PIPELINE ----------------------------------------------
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rATOM <= 2'h0;
+ rBRA <= 1'h0;
+ rDLY <= 1'h0;
+ rIPC <= 30'h0;
+ rPC <= 30'h0;
+ rPCLNK <= 30'h0;
+ // End of automatics
+ end else if (gena) begin
+ rIPC <= #1 xIPC;
+ rBRA <= #1 xBRA;
+ rPC <= #1 xPC;
+ rPCLNK <= #1 xPCLNK;
+ rDLY <= #1 xDLY;
+ rATOM <= #1 xATOM;
+ end
+
+endmodule // aeMB_bpcu
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bsft.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bsft.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_bsft.v
2007-11-05 00:37:45 UTC (rev 6810)
@@ -0,0 +1,101 @@
+// $Id: aeMB_bsft.v,v 1.2 2007/11/03 08:34:54 sybreon Exp $
+//
+// AEMB SINGLE CYCLE 32'BIT BARREL SHIFTER
+//
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public License
+// as published by the Free Software Foundation; either version 2.1 of
+// the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//
+// $Log: aeMB_bsft.v,v $
+// Revision 1.2 2007/11/03 08:34:54 sybreon
+// Minor code cleanup.
+//
+
+module aeMB_bsft (/*AUTOARG*/
+ // Outputs
+ rRES_BSF,
+ // Inputs
+ rOPA, rOPB, rALT
+ );
+
+ output [31:0] rRES_BSF;
+ input [31:0] rOPA, rOPB;
+ input [10:0] rALT;
+
+ reg [31:0] rRES_BSF;
+ reg [31:0] xBSRL, xBSRA, xBSLL;
+
+ // --- LOGICAL LEFT ----------------------------------------------
+ // Infer a logical left barrel shifter.
+
+ always @(/*AUTOSENSE*/rOPA or rOPB)
+ xBSLL <= rOPA << rOPB[4:0];
+
+ // --- LOGICAL RIGHT ---------------------------------------------
+ // Infer a logical right barrel shifter.
+
+ always @(/*AUTOSENSE*/rOPA or rOPB)
+ xBSRL <= rOPA >> rOPB[4:0];
+
+ // --- ARITHMETIC RIGH -------------------------------------------
+ // Infer a arithmetic right barrel shifter.
+
+ always @(/*AUTOSENSE*/rOPA or rOPB)
+ case (rOPB[4:0])
+ 5'd00: xBSRA <= rOPA;
+ 5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};
+ 5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};
+ 5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]};
+ 5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]};
+ 5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]};
+ 5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]};
+ 5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]};
+ 5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]};
+ 5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]};
+ 5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]};
+ 5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]};
+ 5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]};
+ 5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]};
+ 5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]};
+ 5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]};
+ 5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]};
+ 5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]};
+ 5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]};
+ 5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]};
+ 5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]};
+ 5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]};
+ 5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]};
+ 5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]};
+ 5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]};
+ 5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]};
+ 5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]};
+ 5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]};
+ 5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]};
+ 5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};
+ 5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};
+ 5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
+ endcase // case (rOPB[4:0])
+
+ always @(/*AUTOSENSE*/rALT or xBSLL or xBSRA or xBSRL)
+ case (rALT[10:9])
+ 2'd0: rRES_BSF <= xBSRL;
+ 2'd1: rRES_BSF <= xBSRA;
+ 2'd2: rRES_BSF <= xBSLL;
+ default: rRES_BSF <= 32'hX;
+ endcase // case (rALT[10:9])
+
+
+endmodule // aeMB_bsft
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ctrl.v
2007-11-05 00:37:45 UTC (rev 6810)
@@ -0,0 +1,199 @@
+// $Id: aeMB_ctrl.v,v 1.2 2007/11/02 19:20:58 sybreon Exp $
+//
+// AEMB CONTROL UNIT
+//
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public License
+// as published by the Free Software Foundation; either version 2.1 of
+// the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//
+// $Log: aeMB_ctrl.v,v $
+// Revision 1.2 2007/11/02 19:20:58 sybreon
+// Added better (beta) interrupt support.
+// Changed MSR_IE to disabled at reset as per MB docs.
+//
+// Revision 1.1 2007/11/02 03:25:40 sybreon
+// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+// Fixed various minor data hazard bugs.
+// Code compatible with -O0/1/2/3/s generated code.
+//
+
+module aeMB_ctrl (/*AUTOARG*/
+ // Outputs
+ rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, rDWBSTB, dwb_stb_o,
+ dwb_wre_o,
+ // Inputs
+ rXCE, rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE,
+ gclk, grst, gena
+ );
+ // INTERNAL
+ //output [31:2] rPCLNK;
+ output [1:0] rMXDST;
+ output [1:0] rMXSRC, rMXTGT, rMXALT;
+ output [2:0] rMXALU;
+ output [4:0] rRW;
+ output rDWBSTB;
+ input [1:0] rXCE;
+ input rDLY;
+ input [15:0] rIMM;
+ input [10:0] rALT;
+ input [5:0] rOPC;
+ input [4:0] rRD, rRA, rRB;
+ input [31:2] rPC;
+ input rBRA;
+ input rMSR_IE;
+
+ // DATA WISHBONE
+ output dwb_stb_o;
+ output dwb_wre_o;
+
+ // SYSTEM
+ input gclk, grst, gena;
+
+ // --- DECODE INSTRUCTIONS
+ // TODO: Simplify
+
+ wire fSFT = (rOPC == 6'o44);
+ wire fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);
+
+ wire fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
+ wire fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
+ wire fDIV = (rOPC == 6'o22);
+
+ wire fRTD = (rOPC == 6'o55);
+ wire fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
+ wire fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
+ wire fBRA = fBRU & rRA[3];
+
+ wire fIMM = (rOPC == 6'o54);
+ wire fMOV = (rOPC == 6'o45);
+
+ wire fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
+ wire fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
+ wire fLDST = (&rOPC[5:4]);
+
+
+ // --- OPERAND SELECTOR ---------------------------------
+
+ wire fRDWE = |rRW;
+ wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
+ wire fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;
+ wire fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;
+ wire fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;
+
+ assign rMXSRC = (fBRU | fBCC) ? 2'o3 : // PC
+ (fAFWD_M) ? 2'o2: // RAM
+ (fAFWD_R) ? 2'o1: // FWD
+ 2'o0; // REG
+
+ assign rMXTGT = (rOPC[3]) ? 2'o3 : // IMM
+ (fBFWD_M) ? 2'o2 : // RAM
+ (fBFWD_R) ? 2'o1 : // FWD
+ 2'o0; // REG
+
+ assign rMXALT = (fAFWD_M) ? 2'o2 : // RAM
+ (fAFWD_R) ? 2'o1 : // FWD
+ 2'o0; // REG
+
+
+ // --- ALU CONTROL ---------------------------------------
+
+ reg [2:0] rMXALU;
+ always @(/*AUTOSENSE*/fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
+ or fSFT) begin
+ rMXALU <= (fBRA | fMOV) ? 3'o3 :
+ (fSFT) ? 3'o2 :
+ (fLOG) ? 3'o1 :
+ (fMUL) ? 3'o4 :
+ (fBSF) ? 3'o5 :
+ (fDIV) ? 3'o6 :
+ 3'o0;
+ end
+
+
+ // --- RAM CONTROL ---------------------------------------
+
+ reg rDWBSTB, xDWBSTB;
+ reg rDWBWRE, xDWBWRE;
+
+ assign dwb_stb_o = rDWBSTB;
+ assign dwb_wre_o = rDWBWRE;
+
+ // --- DELAY SLOT REGISTERS ------------------------------
+
+ reg [31:2] rPCLNK, xPCLNK;
+ reg [1:0] rMXDST, xMXDST;
+ reg [4:0] rRW, xRW;
+
+ wire fSKIP = (rBRA & !rDLY);
+
+ always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or rXCE)
+ if (fSKIP | |rXCE) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xDWBSTB <= 1'h0;
+ xDWBWRE <= 1'h0;
+ // End of automatics
+ end else begin
+ xDWBSTB <= fLOD | fSTR;
+ xDWBWRE <= fSTR;
+ end
+
+ always @(/*AUTOSENSE*/fBCC or fBRU or fLOD or fRTD or fSKIP or fSTR
+ or rRD or rXCE)
+ if (fSKIP) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xMXDST <= 2'h0;
+ xRW <= 5'h0;
+ // End of automatics
+ end else begin
+ case (rXCE)
+ 2'o2: xMXDST <= 2'o1;
+ default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
+ (fLOD) ? 2'o2 :
+ (fBRU) ? 2'o1 :
+ 2'o0;
+ endcase
+
+ case (rXCE)
+ 2'o2: xRW <= 5'd14;
+ default: xRW <= rRD;
+ endcase
+
+ end // else: !if(fSKIP)
+
+
+ // --- PIPELINE CONTROL DELAY ----------------------------
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rDWBSTB <= 1'h0;
+ rDWBWRE <= 1'h0;
+ rMXDST <= 2'h0;
+ rRW <= 5'h0;
+ // End of automatics
+ end else if (gena) begin
+ //rPCLNK <= #1 xPCLNK;
+ rMXDST <= #1 xMXDST;
+ rRW <= #1 xRW;
+ rDWBSTB <= #1 xDWBSTB;
+ rDWBWRE <= #1 xDWBWRE;
+ end
+
+
+endmodule // aeMB_ctrl
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_edk32.v
2007-11-05 00:37:45 UTC (rev 6810)
@@ -0,0 +1,279 @@
+// $Id: aeMB_edk32.v,v 1.3 2007/11/03 08:34:55 sybreon Exp $
+//
+// AEMB EDK 3.2 Compatible Core
+//
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public License
+// as published by the Free Software Foundation; either version 2.1 of
+// the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//
+// $Log: aeMB_edk32.v,v $
+// Revision 1.3 2007/11/03 08:34:55 sybreon
+// Minor code cleanup.
+//
+// Revision 1.2 2007/11/02 19:20:58 sybreon
+// Added better (beta) interrupt support.
+// Changed MSR_IE to disabled at reset as per MB docs.
+//
+// Revision 1.1 2007/11/02 03:25:40 sybreon
+// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+// Fixed various minor data hazard bugs.
+// Code compatible with -O0/1/2/3/s generated code.
+//
+
+module aeMB_edk32 (/*AUTOARG*/
+ // Outputs
+ iwb_stb_o, iwb_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o,
+ dwb_adr_o,
+ // Inputs
+ sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, dwb_dat_i,
+ dwb_ack_i
+ );
+
+ parameter IW = 32;
+ parameter DW = 32;
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [DW-1:2] dwb_adr_o; // From xecu of aeMB_xecu.v
+ output [31:0] dwb_dat_o; // From regf of aeMB_regf.v
+ output [3:0] dwb_sel_o; // From xecu of
aeMB_xecu.v
+ output dwb_stb_o; // From ctrl of aeMB_ctrl.v
+ output dwb_wre_o; // From ctrl of aeMB_ctrl.v
+ output [IW-1:2] iwb_adr_o; // From bpcu of aeMB_bpcu.v
+ output iwb_stb_o; // From ibuf of aeMB_ibuf.v
+ // End of automatics
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input dwb_ack_i; // To scon of aeMB_scon.v
+ input [31:0] dwb_dat_i; // To regf of
aeMB_regf.v
+ input iwb_ack_i; // To scon of aeMB_scon.v, ...
+ input [31:0] iwb_dat_i; // To ibuf of
aeMB_ibuf.v
+ input sys_clk_i; // To scon of aeMB_scon.v
+ input sys_int_i; // To scon of aeMB_scon.v
+ input sys_rst_i; // To scon of aeMB_scon.v
+ // End of automatics
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire gclk; // From scon of
aeMB_scon.v
+ wire gena; // From scon of
aeMB_scon.v
+ wire grst; // From scon of
aeMB_scon.v
+ wire [10:0] rALT; // From ibuf of aeMB_ibuf.v
+ wire [1:0] rATOM; // From bpcu of aeMB_bpcu.v
+ wire rBRA; // From bpcu of
aeMB_bpcu.v
+ wire rDLY; // From bpcu of
aeMB_bpcu.v
+ wire [31:0] rDWBDI; // From regf of aeMB_regf.v
+ wire [3:0] rDWBSEL; // From xecu of aeMB_xecu.v
+ wire rDWBSTB; // From ctrl of
aeMB_ctrl.v
+ wire [15:0] rIMM; // From ibuf of aeMB_ibuf.v
+ wire rMSR_BIP; // From xecu of
aeMB_xecu.v
+ wire rMSR_IE; // From xecu of
aeMB_xecu.v
+ wire [1:0] rMXALT; // From ctrl of aeMB_ctrl.v
+ wire [2:0] rMXALU; // From ctrl of aeMB_ctrl.v
+ wire [1:0] rMXDST; // From ctrl of aeMB_ctrl.v
+ wire [1:0] rMXSRC; // From ctrl of aeMB_ctrl.v
+ wire [1:0] rMXTGT; // From ctrl of aeMB_ctrl.v
+ wire [5:0] rOPC; // From ibuf of aeMB_ibuf.v
+ wire [31:2] rPC; // From bpcu of aeMB_bpcu.v
+ wire [31:2] rPCLNK; // From bpcu of aeMB_bpcu.v
+ wire [4:0] rRA; // From ibuf of aeMB_ibuf.v
+ wire [4:0] rRB; // From ibuf of aeMB_ibuf.v
+ wire [4:0] rRD; // From ibuf of aeMB_ibuf.v
+ wire [31:0] rREGA; // From regf of aeMB_regf.v
+ wire [31:0] rREGB; // From regf of aeMB_regf.v
+ wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
+ wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
+ wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
+ wire [1:0] rXCE; // From scon of aeMB_scon.v
+ // End of automatics
+
+ wire [31:0] rOPA, rOPB;
+ wire [31:0] rRES_MUL, rRES_BSF;
+
+ // --- OPTIONAL COMPONENTS -----------------------------------
+ // Trade off hardware size/speed for software speed
+
+ aeMB_mult
+ mult (
+ // Outputs
+ .rRES_MUL (rRES_MUL[31:0]),
+ // Inputs
+ .rOPA (rOPA[31:0]),
+ .rOPB (rOPB[31:0]));
+
+ aeMB_bsft
+ bsft (
+ // Outputs
+ .rRES_BSF (rRES_BSF[31:0]),
+ // Inputs
+ .rOPA (rOPA[31:0]),
+ .rOPB (rOPB[31:0]),
+ .rALT (rALT[10:0]));
+
+
+ // --- NON-OPTIONAL COMPONENTS -------------------------------
+ // These components make up the main AEMB processor.
+
+ aeMB_scon
+ scon (/*AUTOINST*/
+ // Outputs
+ .rXCE (rXCE[1:0]),
+ .grst (grst),
+ .gclk (gclk),
+ .gena (gena),
+ // Inputs
+ .rOPC (rOPC[5:0]),
+ .rATOM (rATOM[1:0]),
+ .rDWBSTB (rDWBSTB),
+ .dwb_ack_i (dwb_ack_i),
+ .iwb_ack_i (iwb_ack_i),
+ .rMSR_IE (rMSR_IE),
+ .rMSR_BIP (rMSR_BIP),
+ .rBRA (rBRA),
+ .rDLY (rDLY),
+ .sys_clk_i (sys_clk_i),
+ .sys_rst_i (sys_rst_i),
+ .sys_int_i (sys_int_i));
+
+ aeMB_ibuf
+ ibuf (/*AUTOINST*/
+ // Outputs
+ .rIMM (rIMM[15:0]),
+ .rRA (rRA[4:0]),
+ .rRD (rRD[4:0]),
+ .rRB (rRB[4:0]),
+ .rALT (rALT[10:0]),
+ .rOPC (rOPC[5:0]),
+ .rSIMM (rSIMM[31:0]),
+ .iwb_stb_o (iwb_stb_o),
+ // Inputs
+ .rBRA (rBRA),
+ .rXCE (rXCE[1:0]),
+ .iwb_dat_i (iwb_dat_i[31:0]),
+ .iwb_ack_i (iwb_ack_i),
+ .gclk (gclk),
+ .grst (grst),
+ .gena (gena));
+
+ aeMB_ctrl
+ ctrl (/*AUTOINST*/
+ // Outputs
+ .rMXDST (rMXDST[1:0]),
+ .rMXSRC (rMXSRC[1:0]),
+ .rMXTGT (rMXTGT[1:0]),
+ .rMXALT (rMXALT[1:0]),
+ .rMXALU (rMXALU[2:0]),
+ .rRW (rRW[4:0]),
+ .rDWBSTB (rDWBSTB),
+ .dwb_stb_o (dwb_stb_o),
+ .dwb_wre_o (dwb_wre_o),
+ // Inputs
+ .rXCE (rXCE[1:0]),
+ .rDLY (rDLY),
+ .rIMM (rIMM[15:0]),
+ .rALT (rALT[10:0]),
+ .rOPC (rOPC[5:0]),
+ .rRD (rRD[4:0]),
+ .rRA (rRA[4:0]),
+ .rRB (rRB[4:0]),
+ .rPC (rPC[31:2]),
+ .rBRA (rBRA),
+ .rMSR_IE (rMSR_IE),
+ .gclk (gclk),
+ .grst (grst),
+ .gena (gena));
+
+ aeMB_bpcu #(IW)
+ bpcu (/*AUTOINST*/
+ // Outputs
+ .iwb_adr_o (iwb_adr_o[IW-1:2]),
+ .rPC (rPC[31:2]),
+ .rPCLNK (rPCLNK[31:2]),
+ .rBRA (rBRA),
+ .rDLY (rDLY),
+ .rATOM (rATOM[1:0]),
+ // Inputs
+ .rMXALT (rMXALT[1:0]),
+ .rOPC (rOPC[5:0]),
+ .rRD (rRD[4:0]),
+ .rRA (rRA[4:0]),
+ .rRESULT (rRESULT[31:0]),
+ .rDWBDI (rDWBDI[31:0]),
+ .rREGA (rREGA[31:0]),
+ .rXCE (rXCE[1:0]),
+ .gclk (gclk),
+ .grst (grst),
+ .gena (gena));
+
+ aeMB_regf
+ regf (/*AUTOINST*/
+ // Outputs
+ .rREGA (rREGA[31:0]),
+ .rREGB (rREGB[31:0]),
+ .rDWBDI (rDWBDI[31:0]),
+ .dwb_dat_o (dwb_dat_o[31:0]),
+ // Inputs
+ .rOPC (rOPC[5:0]),
+ .rRA (rRA[4:0]),
+ .rRB (rRB[4:0]),
+ .rRW (rRW[4:0]),
+ .rRD (rRD[4:0]),
+ .rMXDST (rMXDST[1:0]),
+ .rPCLNK (rPCLNK[31:2]),
+ .rRESULT (rRESULT[31:0]),
+ .rDWBSEL (rDWBSEL[3:0]),
+ .rBRA (rBRA),
+ .rDLY (rDLY),
+ .dwb_dat_i (dwb_dat_i[31:0]),
+ .gclk (gclk),
+ .grst (grst),
+ .gena (gena));
+
+ aeMB_xecu #(DW)
+ xecu (
+ .rOPA (rOPA[31:0]),
+ .rOPB (rOPB[31:0]),
+ /*AUTOINST*/
+ // Outputs
+ .dwb_adr_o (dwb_adr_o[DW-1:2]),
+ .dwb_sel_o (dwb_sel_o[3:0]),
+ .rRESULT (rRESULT[31:0]),
+ .rDWBSEL (rDWBSEL[3:0]),
+ .rMSR_IE (rMSR_IE),
+ .rMSR_BIP (rMSR_BIP),
+ // Inputs
+ .rXCE (rXCE[1:0]),
+ .rREGA (rREGA[31:0]),
+ .rREGB (rREGB[31:0]),
+ .rMXSRC (rMXSRC[1:0]),
+ .rMXTGT (rMXTGT[1:0]),
+ .rRA (rRA[4:0]),
+ .rMXALU (rMXALU[2:0]),
+ .rBRA (rBRA),
+ .rDLY (rDLY),
+ .rSIMM (rSIMM[31:0]),
+ .rIMM (rIMM[15:0]),
+ .rOPC (rOPC[5:0]),
+ .rRD (rRD[4:0]),
+ .rDWBDI (rDWBDI[31:0]),
+ .rPC (rPC[31:2]),
+ .rRES_MUL (rRES_MUL[31:0]),
+ .rRES_BSF (rRES_BSF[31:0]),
+ .gclk (gclk),
+ .grst (grst),
+ .gena (gena));
+
+
+endmodule // aeMB_edk32
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_ibuf.v
2007-11-05 00:37:45 UTC (rev 6810)
@@ -0,0 +1,98 @@
+// $Id: aeMB_ibuf.v,v 1.3 2007/11/03 08:34:55 sybreon Exp $
+//
+// AEMB INSTRUCTION BUFFER
+//
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public License
+// as published by the Free Software Foundation; either version 2.1 of
+// the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//
+// $Log: aeMB_ibuf.v,v $
+// Revision 1.3 2007/11/03 08:34:55 sybreon
+// Minor code cleanup.
+//
+// Revision 1.2 2007/11/02 19:20:58 sybreon
+// Added better (beta) interrupt support.
+// Changed MSR_IE to disabled at reset as per MB docs.
+//
+// Revision 1.1 2007/11/02 03:25:40 sybreon
+// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+// Fixed various minor data hazard bugs.
+// Code compatible with -O0/1/2/3/s generated code.
+//
+
+module aeMB_ibuf (/*AUTOARG*/
+ // Outputs
+ rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, iwb_stb_o,
+ // Inputs
+ rBRA, rXCE, iwb_dat_i, iwb_ack_i, gclk, grst, gena
+ );
+ // INTERNAL
+ output [15:0] rIMM;
+ output [4:0] rRA, rRD, rRB;
+ output [10:0] rALT;
+ output [5:0] rOPC;
+ output [31:0] rSIMM;
+ input rBRA;
+ input [1:0] rXCE;
+
+ // INST WISHBONE
+ output iwb_stb_o;
+ input [31:0] iwb_dat_i;
+ input iwb_ack_i;
+
+ // SYSTEM
+ input gclk, grst, gena;
+
+ reg [15:0] rIMM;
+ reg [4:0] rRA, rRD;
+ reg [5:0] rOPC;
+
+ // FIXME: Endian
+ wire [31:0] wIDAT = iwb_dat_i;
+ assign {rRB, rALT} = rIMM;
+
+ // TODO: Assign to FIFO not full.
+ assign iwb_stb_o = 1'b1;
+
+ reg [31:0] rSIMM, xSIMM;
+ wire fIMM = (rOPC == 6'o54);
+
+ reg [31:0] xIREG;
+
+ // DELAY SLOT
+ always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or rXCE or wIDAT) begin
+ xIREG <= (rBRA | |rXCE) ? 32'h88000000 : wIDAT;
+ xSIMM <= (!fIMM | rBRA | |rXCE) ? { {(16){wIDAT[15]}}, wIDAT[15:0]} :
{rIMM, wIDAT[15:0]};
+ end
+
+ // Synchronous
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rIMM <= 16'h0;
+ rOPC <= 6'h0;
+ rRA <= 5'h0;
+ rRD <= 5'h0;
+ rSIMM <= 32'h0;
+ // End of automatics
+ end else if (gena) begin
+ {rOPC, rRD, rRA, rIMM} <= #1 xIREG;
+ rSIMM <= #1 xSIMM;
+ end
+
+
+endmodule // aeMB_ibuf
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_mult.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_mult.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_mult.v
2007-11-05 00:37:45 UTC (rev 6810)
@@ -0,0 +1,41 @@
+// $Id: aeMB_mult.v,v 1.2 2007/11/03 08:34:55 sybreon Exp $
+//
+// AEMB SINGLE CYCLE 32'BIT MULTIPLIER
+//
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public License
+// as published by the Free Software Foundation; either version 2.1 of
+// the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//
+// $Log: aeMB_mult.v,v $
+// Revision 1.2 2007/11/03 08:34:55 sybreon
+// Minor code cleanup.
+//
+
+module aeMB_mult (/*AUTOARG*/
+ // Outputs
+ rRES_MUL,
+ // Inputs
+ rOPA, rOPB
+ );
+
+ // INTERNAL
+ output [31:0] rRES_MUL;
+
+ input [31:0] rOPA, rOPB;
+
+ assign rRES_MUL = (rOPA * rOPB);
+
+endmodule // aeMB_mult
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regf.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regf.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regf.v
2007-11-05 00:37:45 UTC (rev 6810)
@@ -0,0 +1,161 @@
+// $Id: aeMB_regf.v,v 1.1 2007/11/02 03:25:41 sybreon Exp $
+//
+// AEMB REGISTER FILE
+//
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public License
+// as published by the Free Software Foundation; either version 2.1 of
+// the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//
+// $Log: aeMB_regf.v,v $
+// Revision 1.1 2007/11/02 03:25:41 sybreon
+// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+// Fixed various minor data hazard bugs.
+// Code compatible with -O0/1/2/3/s generated code.
+//
+
+module aeMB_regf (/*AUTOARG*/
+ // Outputs
+ rREGA, rREGB, rDWBDI, dwb_dat_o,
+ // Inputs
+ rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
+ rDLY, dwb_dat_i, gclk, grst, gena
+ );
+ // INTERNAL
+ output [31:0] rREGA, rREGB;
+ output [31:0] rDWBDI;
+ input [5:0] rOPC;
+ input [4:0] rRA, rRB, rRW, rRD;
+ input [1:0] rMXDST;
+ input [31:2] rPCLNK;
+ input [31:0] rRESULT;
+ input [3:0] rDWBSEL;
+ input rBRA, rDLY;
+
+ // DATA WISHBONE
+ output [31:0] dwb_dat_o;
+ input [31:0] dwb_dat_i;
+
+ // SYSTEM
+ input gclk, grst, gena;
+
+ // --- LOAD SIZER ----------------------------------------------
+ // Moves the data bytes around depending on the size of the
+ // operation.
+
+ wire [31:0] wDWBDI = dwb_dat_i; // FIXME: Endian
+ reg [31:0] rDWBDI;
+
+ always @(/*AUTOSENSE*/rDWBSEL or wDWBDI)
+ case (rDWBSEL)
+ // 8'bit
+ 4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
+ 4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
+ 4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
+ 4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]};
+ // 16'bit
+ 4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
+ 4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
+ // 32'bit
+ 4'hF: rDWBDI <= wDWBDI;
+ // Undefined
+ default: rDWBDI <= 32'hX;
+ endcase
+
+ // --- GENERAL PURPOSE REGISTERS (R0-R31) -----------------------
+ // LUT RAM implementation is smaller and faster. R0 gets written
+ // during reset with 0x00 and doesn't change after.
+
+ reg [31:0] mARAM[0:31],
+ mBRAM[0:31],
+ mDRAM[0:31];
+
+ wire [31:0] rREGW = mDRAM[rRW];
+ wire [31:0] rREGD = mDRAM[rRD];
+ assign rREGA = mARAM[rRA];
+ assign rREGB = mBRAM[rRB];
+
+ wire fRDWE = |rRW;
+
+ reg [31:0] xWDAT;
+
+ always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW
+ or rRESULT)
+ case (rMXDST)
+ 2'o2: xWDAT <= rDWBDI;
+ 2'o1: xWDAT <= {rPCLNK, 2'o0};
+ 2'o0: xWDAT <= rRESULT;
+ 2'o3: xWDAT <= rREGW; // No change
+ endcase // case (rMXDST)
+
+ always @(posedge gclk)
+ if (grst | fRDWE) begin
+ mARAM[rRW] <= xWDAT;
+ mBRAM[rRW] <= xWDAT;
+ mDRAM[rRW] <= xWDAT;
+ end
+
+ // --- STORE SIZER ---------------------------------------------
+ // Replicates the data bytes across depending on the size of the
+ // operation.
+
+ wire [31:0] xDST;
+ wire fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
+ wire fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;
+ reg [31:0] rDWBDO, xDWBDO;
+
+ assign dwb_dat_o = rDWBDO;
+ assign xDST = (fDFWD_M) ? rDWBDI :
+ (fDFWD_R) ? rRESULT :
+ rREGD;
+
+ always @(/*AUTOSENSE*/rOPC or xDST)
+ case (rOPC[1:0])
+ // 8'bit
+ 2'h0: xDWBDO <= {(4){xDST[7:0]}};
+ // 16'bit
+ 2'h1: xDWBDO <= {(2){xDST[15:0]}};
+ // 32'bit
+ 2'h2: xDWBDO <= xDST;
+ default: xDWBDO <= 32'hX;
+ endcase // case (rOPC[1:0])
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rDWBDO <= 32'h0;
+ // End of automatics
+ end else if (gena) begin
+ rDWBDO <= #1 xDWBDO;
+ end
+
+ // --- SIMULATION ONLY ------------------------------------------
+ // Randomise memory to simulate real-world memory
+ // synopsys translate_off
+
+ integer i;
+ initial begin
+ for (i=0; i<32; i=i+1) begin
+ mARAM[i] <= $random;
+ mBRAM[i] <= $random;
+ mDRAM[i] <= $random;
+ end
+ end
+
+ // synopsys translate_on
+
+
+endmodule // aeMB_regf
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_scon.v
2007-11-05 00:37:45 UTC (rev 6810)
@@ -0,0 +1,116 @@
+// $Id: aeMB_scon.v,v 1.2 2007/11/02 19:20:58 sybreon Exp $
+//
+// AEMB SYSTEM CONTROL UNIT
+//
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public License
+// as published by the Free Software Foundation; either version 2.1 of
+// the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//
+// $Log: aeMB_scon.v,v $
+// Revision 1.2 2007/11/02 19:20:58 sybreon
+// Added better (beta) interrupt support.
+// Changed MSR_IE to disabled at reset as per MB docs.
+//
+// Revision 1.1 2007/11/02 03:25:41 sybreon
+// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+// Fixed various minor data hazard bugs.
+// Code compatible with -O0/1/2/3/s generated code.
+//
+
+module aeMB_scon (/*AUTOARG*/
+ // Outputs
+ rXCE, grst, gclk, gena,
+ // Inputs
+ rOPC, rATOM, rDWBSTB, dwb_ack_i, iwb_ack_i, rMSR_IE, rMSR_BIP,
+ rBRA, rDLY, sys_clk_i, sys_rst_i, sys_int_i
+ );
+
+ // INTERNAL
+ output [1:0] rXCE;
+ input [5:0] rOPC;
+ input [1:0] rATOM;
+
+ input rDWBSTB;
+ input dwb_ack_i;
+ input iwb_ack_i;
+ input rMSR_IE;
+ input rMSR_BIP;
+
+ input rBRA, rDLY;
+
+ // SYSTEM
+ output grst, gclk, gena;
+ input sys_clk_i, sys_rst_i;
+ input sys_int_i;
+
+
+ assign gclk = sys_clk_i;
+
+ assign gena = !((rDWBSTB ^ dwb_ack_i) | !iwb_ack_i);
+
+ // --- INTERRUPT LATCH ---------------------------------
+
+ reg rFINT;
+ reg [1:0] rDINT;
+ wire wSHOT = rDINT[0] & !rDINT[1] & sys_int_i; // +Edge
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rDINT <= 2'h0;
+ // End of automatics
+ end else if (rMSR_IE) begin
+ rDINT <= #1 {rDINT[0], sys_int_i};
+ end
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rFINT <= 1'h0;
+ // End of automatics
+ end else if (gena) begin
+ rFINT <= (rXCE == 2'o2) ? 1'b0 : (rFINT | wSHOT);
+ end
+
+ // --- EXCEPTION PROCESSING ----------------------------
+
+ reg [1:0] rXCE;
+
+ always @(/*AUTOSENSE*/rATOM or rFINT or rMSR_BIP or rMSR_IE)
+ case (rATOM)
+ default: rXCE <= (!rMSR_BIP & rMSR_IE & rFINT) ? 2'o2 :
+ 2'o0;
+ 2'o0, 2'o3: rXCE <= 0;
+ endcase // case (rATOM)
+
+
+ // --- RESET SYNCHRONISER ------------------------------
+
+ reg [1:0] rRST;
+ assign grst = sys_rst_i;
+
+ always @(posedge sys_clk_i)
+ if (!sys_rst_i) begin
+ rRST <= 2'o3;
+ /*AUTORESET*/
+ end else begin
+ rRST <= #1 {rRST[0], !sys_rst_i};
+ end
+
+
+endmodule // aeMB_scon
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_xecu.v
2007-11-05 00:37:45 UTC (rev 6810)
@@ -0,0 +1,276 @@
+// $Id: aeMB_xecu.v,v 1.3 2007/11/03 08:34:55 sybreon Exp $
+//
+// AEMB MAIN EXECUTION ALU
+//
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public License
+// as published by the Free Software Foundation; either version 2.1 of
+// the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful, but
+// WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+// USA
+//
+// $Log: aeMB_xecu.v,v $
+// Revision 1.3 2007/11/03 08:34:55 sybreon
+// Minor code cleanup.
+//
+// Revision 1.2 2007/11/02 19:20:58 sybreon
+// Added better (beta) interrupt support.
+// Changed MSR_IE to disabled at reset as per MB docs.
+//
+// Revision 1.1 2007/11/02 03:25:41 sybreon
+// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+// Fixed various minor data hazard bugs.
+// Code compatible with -O0/1/2/3/s generated code.
+//
+
+module aeMB_xecu (/*AUTOARG*/
+ // Outputs
+ dwb_adr_o, dwb_sel_o, rRESULT, rOPA, rOPB, rDWBSEL, rMSR_IE,
+ rMSR_BIP,
+ // Inputs
+ rXCE, rREGA, rREGB, rMXSRC, rMXTGT, rRA, rMXALU, rBRA, rDLY, rSIMM,
+ rIMM, rOPC, rRD, rDWBDI, rPC, rRES_MUL, rRES_BSF, gclk, grst, gena
+ );
+ parameter DW=32;
+
+ // DATA WISHBONE
+ output [DW-1:2] dwb_adr_o;
+ output [3:0] dwb_sel_o;
+
+ // INTERNAL
+ output [31:0] rRESULT;
+ output [31:0] rOPA, rOPB;
+ output [3:0] rDWBSEL;
+ output rMSR_IE;
+ output rMSR_BIP;
+ input [1:0] rXCE;
+ input [31:0] rREGA, rREGB;
+ input [1:0] rMXSRC, rMXTGT;
+ input [4:0] rRA;
+ input [2:0] rMXALU;
+ input rBRA, rDLY;
+
+ //input [1:0] rXCE;
+ input [31:0] rSIMM;
+ input [15:0] rIMM;
+ input [5:0] rOPC;
+ input [4:0] rRD;
+ input [31:0] rDWBDI;
+ input [31:2] rPC;
+ input [31:0] rRES_MUL; // External Multiplier
+ input [31:0] rRES_BSF; // External Barrel Shifter
+
+ // SYSTEM
+ input gclk, grst, gena;
+
+ reg rMSR_C, xMSR_C;
+ reg rMSR_IE, xMSR_IE;
+ reg rMSR_BE, xMSR_BE;
+ reg rMSR_BIP, xMSR_BIP;
+
+ wire fSKIP = rBRA & !rDLY;
+
+ // --- OPERAND SELECT
+
+ reg [31:0] rOPA, rOPB;
+ always @(/*AUTOSENSE*/rDWBDI or rMXSRC or rPC or rREGA or rRESULT)
+ case (rMXSRC)
+ 2'o0: rOPA <= rREGA;
+ 2'o1: rOPA <= rRESULT;
+ 2'o2: rOPA <= rDWBDI;
+ 2'o3: rOPA <= {rPC, 2'o0};
+ endcase // case (rMXSRC)
+
+ always @(/*AUTOSENSE*/rDWBDI or rMXTGT or rREGB or rRESULT or rSIMM)
+ case (rMXTGT)
+ 2'o0: rOPB <= rREGB;
+ 2'o1: rOPB <= rRESULT;
+ 2'o2: rOPB <= rDWBDI;
+ 2'o3: rOPB <= rSIMM;
+ endcase // case (rMXTGT)
+
+ // --- ADD/SUB SELECTOR ----
+ // TODO: Refactor
+ // TODO: Verify signed compare
+
+ wire wADDC, wSUBC, wRES_AC, wCMPC, wOPC;
+ wire [31:0] wADD, wSUB, wRES_A, wCMP, wOPX;
+
+ wire wCMPU = (rOPA > rOPB);
+ wire wCMPF = (rIMM[1]) ? wCMPU :
+ ((wCMPU & ~(rOPB[31] ^ rOPA[31])) | (rOPB[31] &
~rOPA[31]));
+
+ assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
+ assign wOPX = (rOPC[0] & !rOPC[5]) ? ~rOPA : rOPA ;
+ assign wOPC = ((rMSR_C & rOPC[1]) | (rOPC[0] & !rOPC[1])) &
(!rOPC[5] & ~&rOPC[5:4]);
+
+ assign {wSUBC,wSUB} = {wADDC,wADD};
+ assign {wADDC,wADD} = (rOPB + wOPX) + wOPC;
+
+ reg rRES_ADDC;
+ reg [31:0] rRES_ADD;
+ always @(rIMM or rOPC or wADD or wADDC or wCMP
+ or wCMPC or wSUB or wSUBC)
+ case ({rOPC[3],rOPC[0],rIMM[0]})
+ 4'h2, 4'h6, 4'h7: {rRES_ADDC,rRES_ADD} <= #1 {~wSUBC,wSUB}; // SUB
+ 4'h3: {rRES_ADDC,rRES_ADD} <= #1 {~wCMPC,wCMP}; // CMP
+ default: {rRES_ADDC,rRES_ADD} <= #1 {wADDC,wADD};
+ endcase // case ({rOPC[3],rOPC[0],rIMM[0]})
+
+ // --- LOGIC SELECTOR ---
+
+ reg [31:0] rRES_LOG;
+ always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
+ case (rOPC[1:0])
+ 2'o0: rRES_LOG <= #1 rOPA | rOPB;
+ 2'o1: rRES_LOG <= #1 rOPA & rOPB;
+ 2'o2: rRES_LOG <= #1 rOPA ^ rOPB;
+ 2'o3: rRES_LOG <= #1 rOPA & ~rOPB;
+ endcase // case (rOPC[1:0])
+
+ // --- SHIFT SELECTOR ---
+
+ reg [31:0] rRES_SFT;
+ reg rRES_SFTC;
+
+ always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
+ case (rIMM[6:5])
+ 2'o0: {rRES_SFT, rRES_SFTC} <= #1 {rOPA[31],rOPA[31:0]};
+ 2'o1: {rRES_SFT, rRES_SFTC} <= #1 {rMSR_C,rOPA[31:0]};
+ 2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]};
+ 2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}},
rOPA[15:0], rMSR_C} :
+ { {(24){rOPA[7]}}, rOPA[7:0], rMSR_C};
+ endcase // case (rIMM[6:5])
+
+ // --- MOVE SELECTOR ---
+
+ wire [31:0] wMSR = {rMSR_C, 3'o0,
+ 20'h0ED32,
+ 4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE};
+ wire fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
+ wire fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
+ reg [31:0] rRES_MOV;
+ always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC or rRA
+ or wMSR)
+ rRES_MOV <= (fMFSR) ? wMSR :
+ (fMFPC) ? rPC :
+ (rRA[3]) ? rOPB :
+ rOPA;
+
+
+ // --- MSR REGISTER -----------------
+
+ // C
+ wire fMTS = (rOPC == 6'o45) & rIMM[14];
+ wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
+
+ always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
+ or rOPA or rRES_ADDC or rRES_SFTC or rXCE)
+ if (fSKIP | |rXCE) begin
+ xMSR_C <= rMSR_C;
+ end else
+ case (rMXALU)
+ 3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;
+ 3'o1: xMSR_C <= rMSR_C; // LOGIC
+ 3'o2: xMSR_C <= rRES_SFTC; // SHIFT
+ 3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
+ 3'o4: xMSR_C <= rMSR_C;
+ 3'o5: xMSR_C <= rMSR_C;
+ default: xMSR_C <= 1'hX;
+ endcase
+
+ // IE/BIP/BE
+ wire fRTID = (rOPC == 6'o55) & rRD[0];
+ wire fRTBD = (rOPC == 6'o55) & rRD[1];
+ wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA[4:2] ==
3'o3);
+
+ always @(/*AUTOSENSE*/fMTS or fRTID or rMSR_IE or rOPA or rXCE)
+ xMSR_IE <= (rXCE == 2'o2) ? 1'b0 :
+ (fRTID) ? 1'b1 :
+ (fMTS) ? rOPA[1] :
+ rMSR_IE;
+
+ always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA)
+ xMSR_BIP <= (fBRK) ? 1'b1 :
+ (fRTBD) ? 1'b0 :
+ (fMTS) ? rOPA[3] :
+ rMSR_BIP;
+
+ always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA)
+ xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE;
+
+ // --- RESULT SELECTOR
+
+ reg [31:0] rRESULT, xRESULT;
+
+ // RESULT
+ always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF
+ or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT)
+ if (fSKIP)
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xRESULT <= 32'h0;
+ // End of automatics
+ else
+ case (rMXALU)
+ 3'o0: xRESULT <= rRES_ADD;
+ 3'o1: xRESULT <= rRES_LOG;
+ 3'o2: xRESULT <= rRES_SFT;
+ 3'o3: xRESULT <= rRES_MOV;
+ 3'o4: xRESULT <= rRES_MUL;
+ 3'o5: xRESULT <= rRES_BSF;
+ default: xRESULT <= 32'hX;
+ endcase // case (rMXALU)
+
+ // --- DATA WISHBONE -----
+
+ reg [3:0] rDWBSEL, xDWBSEL;
+ assign dwb_adr_o = rRESULT[DW-1:2];
+ assign dwb_sel_o = rDWBSEL;
+
+ always @(/*AUTOSENSE*/rOPC or wADD)
+ case (rOPC[1:0])
+ 2'o0: case (wADD[1:0])
+ 2'o0: xDWBSEL <= 4'h8;
+ 2'o1: xDWBSEL <= 4'h4;
+ 2'o2: xDWBSEL <= 4'h2;
+ 2'o3: xDWBSEL <= 4'h1;
+ endcase // case (wADD[1:0])
+ 2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC;
+ 2'o2: xDWBSEL <= 4'hF;
+ default: xDWBSEL <= 4'hX;
+ endcase // case (rOPC[1:0])
+
+ // --- SYNC ---
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rDWBSEL <= 4'h0;
+ rMSR_BE <= 1'h0;
+ rMSR_BIP <= 1'h0;
+ rMSR_C <= 1'h0;
+ rMSR_IE <= 1'h0;
+ rRESULT <= 32'h0;
+ // End of automatics
+ end else if (gena) begin
+ rRESULT <= #1 xRESULT;
+ rDWBSEL <= #1 xDWBSEL;
+ rMSR_C <= #1 xMSR_C;
+ rMSR_IE <= #1 xMSR_IE;
+ rMSR_BE <= #1 xMSR_BE;
+ rMSR_BIP <= #1 xMSR_BIP;
+ end
+
+endmodule // aeMB_xecu
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