[Commit-gnuradio] r6796 - gnuradio/branches/developers/matt/u2f/top/u2_basic

[matt]

Author: matt
Date: 2007-11-02 18:22:59 -0600 (Fri, 02 Nov 2007)
New Revision: 6796

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
control of PHY_RESETn and phy debugging pins


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-11-02 22:08:57 UTC (rev 6795)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-11-03 00:22:59 UTC (rev 6796)
@@ -42,7 +42,7 @@
    inout MDIO,
    output MDC,
    input PHY_INTn,   // open drain
-   input PHY_RESETn,
+   output PHY_RESETn,
    input PHY_CLK,   // possibly use on-board osc
 
    // SERDES
@@ -127,7 +127,9 @@
 
    wire [31:0]         status, status_b0, status_b1, status_b2, status_b3, 
status_b4, status_b5, status_b6, status_b7;
    wire        bus_error, spi_int, i2c_int, timer_int, buffer_int, proc_int, 
overrun, underrun;
-   
+
+   wire [31:0]         debug_wb;
+   wire [15:0]         debug_gmii_1, debug_gmii_2;
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
@@ -319,7 +321,8 @@
    nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
                 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
                 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
-                .internal_sig(),.debug(),.gpio( /* {io_tx,io_rx} */ ) );
+                .debug_0( {debug_wb[15:0],debug_wb[31:16]} 
),.debug_1({debug_gmii_2,debug_gmii_1}),
+                .gpio( {io_tx,io_rx} ) );
    assign       s4_err = 1'b0;
    assign       s4_rty = 1'b0;
 
@@ -357,8 +360,11 @@
    wire [7:0]   clock_outs, serdes_outs, adc_outs, misc_outs;
    assign       {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
    assign       {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = 
serdes_outs[3:0];
-   assign       { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0];
+   assign       {adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0];
    assign       {led2, led1} = misc_outs[1:0];
+
+   wire         phy_reset;
+   assign       PHY_RESETn = ~phy_reset;
    
    setting_reg #(.my_addr(0)) sr_clk 
(.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
                                      
.in(set_data),.out(clock_outs),.changed());
@@ -368,6 +374,8 @@
                                      .in(set_data),.out(adc_outs),.changed());
    setting_reg #(.my_addr(3)) sr_led 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
                                      .in(set_data),.out(misc_outs),.changed());
+   setting_reg #(.my_addr(4)) sr_phy 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+                                     .in(set_data),.out(phy_reset),.changed());
 
    // /////////////////////////////////////////////////////////////////////////
    // Ethernet MAC  Slave #6
@@ -509,15 +517,16 @@
    
    wire [31:0] debug_new = {{ram_loader_done ? {iram_rd_adr[15:0]} : 
iram_wr_adr[15:0]},
                            {3'b0,ram_loader_done,clock_ready, wb_rst, 
proc_int,timer_int},
-                           {8'b0} };
+                           {1'b0, 
GMII_TX_CLK,clk_to_mac,PHY_CLK,MDC,MDIO,PHY_INTn,PHY_RESETn} };
+   /* MAC_top.U_eth_miim.MdoEn */
    
    wire [31:0] debug_iram_dat = ram_loader_done ? iram_rd_dat : iram_wr_dat;
+   
+   assign      debug_wb = {m0_adr[15:0], m0_sel[3:0], m0_ack, m0_we, m0_stb, 
m0_err};
 
-   wire [31:0] debug_wb = {m0_adr[15:0], m0_sel[3:0], m0_ack, m0_we, m0_stb, 
m0_err};
-   
+   assign      debug_gmii_1 = 
{GMII_COL,GMII_CRS,GMII_RX_CLK,GMII_RX_DV,GMII_RX_ER,GMII_TX_CLK,GMII_TX_EN,GMII_TX_ER,GMII_TXD[7:0]};
+   assign      debug_gmii_2 = 
{GMII_COL,GMII_CRS,GMII_RX_CLK,GMII_RX_DV,GMII_RX_ER,GMII_TX_CLK,GMII_TX_EN,GMII_TX_ER,GMII_RXD[7:0]};
    assign      debug = debug_new;
-   assign      io_rx = debug_wb[31:16];
-   assign      io_tx = debug_wb[15:0];
    
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk;