[Commit-gnuradio] r6791 - gnuradio/branches/developers/matt/u2f/top/u2_fpga

[matt]

Author: matt
Date: 2007-11-02 00:34:29 -0600 (Fri, 02 Nov 2007)
New Revision: 6791

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
Log:
added a proper reset for the DCM after we switch clocks


Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v     
2007-11-02 06:33:08 UTC (rev 6790)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v     
2007-11-02 06:34:29 UTC (rev 6791)
@@ -37,7 +37,7 @@
    inout MDIO,
    output MDC,
    input PHY_INTn,   // open drain
-   input PHY_RESETn,
+   output PHY_RESETn,
    input PHY_CLK,   // possibly use on-board osc
 
    // RAM
@@ -165,9 +165,11 @@
    OBUFDS exp_pps_out_pin 
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
    defparam    exp_pps_out_pin.IOSTANDARD = "LVDS_25";
 
-   //wire      dcm_rst = ~clock_ready;
-   wire        dcm_rst = 1'b0;
+   reg [5:0]   clock_ready_d;
+   always @(posedge aux_clk)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
 
+   wire        dcm_rst = ~&clock_ready_d & |clock_ready_d;
    wire        clk_muxed = clock_ready ? clk_fpga : aux_clk;
    
    // Handle Clocks
@@ -320,9 +322,3 @@
                     .io_rx             (io_rx[15:0]));
    
 endmodule // u2_fpga_top
-
-// Local Variables:
-// verilog-library-directories:("." "subdir" "subdir2")
-// 
verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
-// verilog-library-extensions:(".v" ".h")
-// End: