[Commit-gnuradio] r6775 - in gnuradio/branches/developers/jcorgan/t195/usrp/fpga: rbf/rev2 rbf/rev4 sdr_lib

[jcorgan]

Author: jcorgan
Date: 2007-11-01 17:53:51 -0600 (Thu, 01 Nov 2007)
New Revision: 6775

Modified:
   
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf
   gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev2/std_4rx_0tx.rbf
   
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf
   gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev4/std_4rx_0tx.rbf
   gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v
Log:
Fixes ticket:195, synthesized with 7.1SP1.

Modified: 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev2/std_4rx_0tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev4/std_4rx_0tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v
===================================================================
--- gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v     
2007-11-01 20:17:12 UTC (rev 6774)
+++ gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v     
2007-11-01 23:53:51 UTC (rev 6775)
@@ -104,6 +104,28 @@
        .aclr ( reset ) );
 
    // DSP Write Side of FIFO
+   reg [15:0] ch_0_reg;
+   reg [15:0] ch_1_reg;
+   reg [15:0] ch_2_reg;
+   reg [15:0] ch_3_reg;
+   reg [15:0] ch_4_reg;
+   reg [15:0] ch_5_reg;
+   reg [15:0] ch_6_reg;
+   reg [15:0] ch_7_reg;
+
+   always @(posedge rxclk)
+     if (rxstrobe)
+       begin
+         ch_0_reg <= ch_0;
+         ch_1_reg <= ch_1;
+         ch_2_reg <= ch_2;
+         ch_3_reg <= ch_3;
+         ch_4_reg <= ch_4;
+         ch_5_reg <= ch_5;
+         ch_6_reg <= ch_6;
+         ch_7_reg <= ch_7;
+       end
+
    reg [3:0] phase;
    always @(posedge rxclk)
      if(reset)
@@ -133,20 +155,20 @@
    always @*
      case(phase)
        4'd1 : begin
-         bottom = ch_0;
-         top = ch_1;
+         bottom = ch_0_reg;
+         top = ch_1_reg;
        end
        4'd2 : begin
-         bottom = ch_2;
-         top = ch_3;
+         bottom = ch_2_reg;
+         top = ch_3_reg;
        end
        4'd3 : begin
-         bottom = ch_4;
-         top = ch_5;
+         bottom = ch_4_reg;
+         top = ch_5_reg;
        end
        4'd4 : begin
-         bottom = ch_6;
-         top = ch_7;
+         bottom = ch_6_reg;
+         top = ch_7_reg;
        end
        default : begin
          top = 16'hFFFF;
@@ -156,14 +178,14 @@
    
    always @*
      case(phase)
-       4'd1 : fifodata_16 = ch_0;
-       4'd2 : fifodata_16 = ch_1;
-       4'd3 : fifodata_16 = ch_2;
-       4'd4 : fifodata_16 = ch_3;
-       4'd5 : fifodata_16 = ch_4;
-       4'd6 : fifodata_16 = ch_5;
-       4'd7 : fifodata_16 = ch_6;
-       4'd8 : fifodata_16 = ch_7;
+       4'd1 : fifodata_16 = ch_0_reg;
+       4'd2 : fifodata_16 = ch_1_reg;
+       4'd3 : fifodata_16 = ch_2_reg;
+       4'd4 : fifodata_16 = ch_3_reg;
+       4'd5 : fifodata_16 = ch_4_reg;
+       4'd6 : fifodata_16 = ch_5_reg;
+       4'd7 : fifodata_16 = ch_6_reg;
+       4'd8 : fifodata_16 = ch_7_reg;
        default : fifodata_16 = 16'hFFFF;
      endcase // case(phase)