[Commit-gnuradio] r6772 - in gnuradio/branches/developers/jcorgan/t195/usrp/fpga: rbf/rev2 rbf/rev4 sdr_lib toplevel/usrp_std

[jcorgan]

Author: jcorgan
Date: 2007-11-01 10:26:15 -0600 (Thu, 01 Nov 2007)
New Revision: 6772

Modified:
   
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf
   
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf
   gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v
   
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/toplevel/usrp_std/usrp_std.v
Log:
Added expanded RX debug bus and synthesized with 7.1SP1.

Modified: 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev2/std_2rxhb_2tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/rbf/rev4/std_2rxhb_2tx.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v
===================================================================
--- gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v     
2007-11-01 08:10:04 UTC (rev 6771)
+++ gnuradio/branches/developers/jcorgan/t195/usrp/fpga/sdr_lib/rx_buffer.v     
2007-11-01 16:26:15 UTC (rev 6772)
@@ -50,7 +50,7 @@
     // Settings, on rxclk also
     input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe,
     input reset_regs, //Only reset registers
-    output [15:0] debugbus
+    output [31:0] debugbus
     );
    
    wire [15:0]           fifodata, fifodata_8;
@@ -183,16 +183,33 @@
      else if(clear_status_dsp)
        rx_overrun_dsp <= 1'b0;
 
-   // RX Debug Bus
-   assign debugbus[0] = RD;
-   assign debugbus[1] = rx_overrun;
-   assign debugbus[2] = read_count[8];
-   assign debugbus[3] = rx_full;
-   assign debugbus[4] = rxstrobe;
-   assign debugbus[5] = usbclk;
-   assign debugbus[6] = have_pkt_rdy;
-   assign debugbus[10:7] = phase;
-   assign debugbus[15:11] = rxfifolevel[4:0];
+   // Debug bus
+   //
+   // 15:0  rxclk  domain => TXA 15:0
+   // 31:16 usbclk domain => RXA 15:0
    
+   assign debugbus[0]     = reset;
+   assign debugbus[1]     = reset_regs;
+   assign debugbus[2]     = rxstrobe;
+   assign debugbus[6:3]   = channels;
+   assign debugbus[7]     = rx_full;
+   assign debugbus[11:8]  = phase;
+   assign debugbus[12]    = ch0_in;
+   assign debugbus[13]    = clear_status_dsp;
+   assign debugbus[14]    = rx_overrun_dsp;
+   assign debugbus[15]    = rxclk;
+
+   assign debugbus[16]    = bus_reset;   
+   assign debugbus[17]    = RD;
+   assign debugbus[18]    = have_pkt_rdy;
+   assign debugbus[19]    = rx_overrun;
+   assign debugbus[20]    = read_count[0];
+   assign debugbus[21]    = read_count[8];
+   assign debugbus[22]    = ch0_out;
+   assign debugbus[23]    = iq_out;
+   assign debugbus[24]    = clear_status;
+   assign debugbus[30:25] = 0;   
+   assign debugbus[31]    = usbclk;
+   
 endmodule // rx_buffer
 

Modified: 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/toplevel/usrp_std/usrp_std.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/toplevel/usrp_std/usrp_std.v
    2007-11-01 08:10:04 UTC (rev 6771)
+++ 
gnuradio/branches/developers/jcorgan/t195/usrp/fpga/toplevel/usrp_std/usrp_std.v
    2007-11-01 16:26:15 UTC (rev 6772)
@@ -93,8 +93,7 @@
    wire [2:0]  tx_numchan;
    
    wire [7:0]  interp_rate, decim_rate;
-   wire [15:0] rx_debugbus;
-   wire [31:0] tx_debugbus;
+   wire [31:0] tx_debugbus, rx_debugbus;
    
    wire        enable_tx, enable_rx;
    wire        tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
@@ -318,7 +317,7 @@
        .tx_empty(tx_empty),
        //.debug_0(rx_a_a),.debug_1(ddc0_in_i),
        .debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]),
-       
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
+       .debug_2(rx_debugbus[15:0]),.debug_3(rx_debugbus[31:16]),
        .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
    
    io_pins io_pins