[Commit-gnuradio] r6770 - gnuradio/branches/developers/matt/u2f/top/u2_sim

[matt]

Author: matt
Date: 2007-10-31 23:19:52 -0600 (Wed, 31 Oct 2007)
New Revision: 6770

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
Log:
changed the printing code, and made the clock dividers match the reality of the 
fpga


Modified: gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v       
2007-11-01 05:19:13 UTC (rev 6769)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v       
2007-11-01 05:19:52 UTC (rev 6770)
@@ -125,20 +125,20 @@
    
    initial clk_to_mac = 0;
    always #4 clk_to_mac = ~clk_to_mac;
-
+   
    wire        div_clk;
    reg [2:0]   div_ctr = 0;
    
-   always @(posedge clk_fpga or negedge clk_fpga)
+   assign      dsp_clk = clock_ready ? clk_fpga : aux_clk;
+   assign      wb_clk = div_clk;
+   
+   always @(posedge dsp_clk or negedge dsp_clk)
      if(div_ctr==5)
        div_ctr = 0;
      else
        div_ctr = div_ctr + 1;
    assign      div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2);
    
-   assign      dsp_clk = clk_fpga;
-   assign      wb_clk = clock_ready ? div_clk : aux_clk;
-
    initial
      $monitor($time, ,clock_ready);
    
@@ -257,25 +257,17 @@
                     .io_rx             (io_rx[15:0]));
 
    // Experimental printf-like function
+   reg               print_edge_det;
    always @(posedge wb_clk)
      begin
-       if((u2_basic.m0_we == 1'd1)&&(u2_basic.m0_adr == 16'hC0F0))
-         $write("%x",u2_basic.m0_dat_i);
-       if((u2_basic.m0_we == 1'd1)&&(u2_basic.m0_adr == 16'hC1F0))
-         $display("%x",u2_basic.m0_dat_i);
-       if((u2_basic.m0_we == 1'd1)&&(u2_basic.m0_adr == 16'hC0F4))
-         $write("%c",u2_basic.m0_dat_i);
-       if((u2_basic.m0_we == 1'd1)&&(u2_basic.m0_adr == 16'hC1F4))
-         $display("%c",u2_basic.m0_dat_i);
-       if((u2_basic.m0_we == 1'd1)&&(u2_basic.m0_adr == 16'hC0F8))
-         $display("");
+       print_edge_det <= io_tx[7];
+       if(!print_edge_det & (io_tx[7] == 1'd1))
+         $write("%c",io_tx[15:8]);
      end
-
+   
    // End the simulation
    always @(posedge wb_clk)
      if((u2_basic.m0_we == 1'd1)&&(u2_basic.m0_adr == 16'hC2F0))
        $finish;
-       
-       
-
+   
 endmodule // u2_sim_top