[Commit-gnuradio] r5866 - gnuradio/branches/developers/matt/u2f/top/u2_basic

[matt]

Author: matt
Date: 2007-06-28 01:05:06 -0600 (Thu, 28 Jun 2007)
New Revision: 5866

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
more connections


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-06-28 07:03:22 UTC (rev 5865)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-06-28 07:05:06 UTC (rev 5866)
@@ -125,12 +125,12 @@
 
    wire [31:0]         ser_debug;
    
-   
//////////////////////////////////////////////////////////////////////////////////////////////////
+   // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
    parameter   aw = 16;  // Address bus width, for byte addressibility, 16 = 
64K byte memory space
    parameter   sw = 4;   // Select width -- 32-bit data bus with 8-bit 
granularity.  
-      
+   
    wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
    wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, 
s2_dat_i, s3_dat_i,
                 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, 
s6_dat_i, s7_dat_i;
@@ -235,16 +235,16 @@
    assign       s0_rty = 1'b0;
 
    // Buffer Pool, slave #1
-   wire         rd0_read, rd0_ready, rd0_done, rd0_empty;
-   wire         rd1_read, rd1_ready, rd1_done, rd1_empty;
-   wire         rd2_read, rd2_ready, rd2_done, rd2_empty;
-   wire         rd3_read, rd3_ready, rd3_done, rd3_empty;
+   wire         rd0_read, rd0_ready, rd0_error, rd0_done, rd0_empty;
+   wire         rd1_read, rd1_ready, rd1_error, rd1_done, rd1_empty;
+   wire         rd2_read, rd2_ready, rd2_error, rd2_done, rd2_empty;
+   wire         rd3_read, rd3_ready, rd3_error, rd3_done, rd3_empty;
    wire [31:0]          rd0_dat, rd1_dat, rd2_dat, rd3_dat;
 
-   wire         wr0_write, wr0_done, wr0_ready, wr0_full;
-   wire         wr1_write, wr1_done, wr1_ready, wr1_full;
-   wire         wr2_write, wr2_done, wr2_ready, wr2_full;
-   wire         wr3_write, wr3_done, wr3_ready, wr3_full;
+   wire         wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full;
+   wire         wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full;
+   wire         wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full;
+   wire         wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full;
    wire [31:0]          wr0_dat, wr1_dat, wr2_dat, wr3_dat;
    
    buffer_pool buffer_pool
@@ -252,17 +252,26 @@
       .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), 
  
       
.wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
    
-      .stream_clk(dsp_clk),.stream_rst(dsp_rst),
+      .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       // Write Interfaces
-      .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(),
-      .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(),
-      .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(),
-      .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(),
+      .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done),
+      .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full),
+      .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done),
+      .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full),
+      .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done),
+      .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full),
+      .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done),
+      .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full),
       // Read Interfaces
-      
.rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty),
-      
.rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty),
-      
.rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty),
-      
.rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty)
+      .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done),
+      .rd0_error_i(rd0_error), .rd0_ready_o(rd0_ready), 
.rd0_empty_o(rd0_empty),
+      .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done),
+      .rd1_error_i(rd1_error), .rd1_ready_o(rd1_ready), 
.rd1_empty_o(rd1_empty),
+      .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done),
+      .rd2_error_i(rd2_error), .rd2_ready_o(rd2_ready), 
.rd2_empty_o(rd2_empty),
+      .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done),
+      .rd3_error_i(rd3_error), .rd3_ready_o(rd3_ready), .rd3_empty_o(rd3_empty)
       );
 
    // SPI -- Slave #2
@@ -366,7 +375,7 @@
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
-      .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done),
+      
.rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done),.rx_error_o(wr1_error),
       .rx_ready_i(wr1_ready),.rx_full_i(wr1_full),
       .overrun() );
    
@@ -374,7 +383,7 @@
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .dac_a(dac_a),.dac_b(dac_b),
-      .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done),
+      
.tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done),.tx_error_o(rd1_error),
       .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty),
       .underrun() );
    
@@ -385,14 +394,15 @@
    serdes_tx serdes_tx
      (.clk(dsp_clk),.rst(dsp_rst),
       
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
-      .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done),
+      
.fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done),.fifo_error_o(rd0_error),
       .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty)
       );
 
    serdes_rx serdes_rx
      (.clk(dsp_clk),.rst(dsp_rst),
       
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
-      
.fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done)
+      
.fifo_data_o(wr0_dat),.fifo_write_o(wr0_write),.fifo_done_o(wr0_done),.fifo_error_o(wr0_error),
+      .fifo_ready_i(wr0_ready),.fifo_full_i(wr0_full)
       );
    
    // Debug Pins