target variable expansion with included make files

[Brad Kemp]

I don't know if this is a bug or this is the way make works
I have appended three makefiles to this email.
The main makefile includes two small makefiles.
Each make file defines variables used in the targets of the other makefile.
The target names are immediatly expanded which causes the first makefile
not to use the variables defined in the second makefile in its target names.
This causes the targets defined in the first makefile to always run the 
associated
rules on every evocation of make.
Is this proper behavior? 
Is there a better approach?
Thanks
Brad Kemp

=========Makefile========
all: do_a do_b

include a.mk
include b.mk

===========a.mk===========

AIMMED:=a_im
ADEFER=a_def

do_a: $(BIMMED)_$(AIMMED) $(BDEFER)_$(ADEFER)


$(BIMMED)_$(AIMMED):
        touch $(BIMMED)_$(AIMMED)
        echo do_a $@ for $(BIMMED)_$(AIMMED)

$(BDEFER)_$(ADEFER):
        touch $(BDEFER)_$(ADEFER)
        echo do_a $@ for $(BDEFER)_$(ADEFER)

==================b.mk==============
BIMMED:=b_im
BDEFER=b_def

do_b: $(AIMMED)_$(BIMMED) $(ADEFER)_$(BDEFER)


$(AIMMED)_$(BIMMED):
        touch $(AIMMED)_$(BIMMED)
        echo do_b $@ for $(AIMMED)_$(BIMMED)

$(ADEFER)_$(BDEFER):
        touch $(ADEFER)_$(BDEFER)
        echo do_b $@ for $(ADEFER)_$(BDEFER)