[BUG???] Targets within variables

[Kyle Moffett]

Please CC me in replies.

I am able to have a variable or variable expression output a single 
target:

> kylemoffett$ cat Makefile
> define some_all
> all:
>         echo 'This is "all" speaking'
> endef
> $(some_all)
>
> kylemoffett$ make all
> echo 'This is "all" speaking'
> This is "all" speaking
>
> kylemoffett$

However, when I attempt to add additional targets within the variable, 
make
appears to treat them as though they were on the same line, even though 
it
still appears to preserve the newlines:

> kylemoffett$ cat Makefile
> define some_all
> all:
>         echo 'This is "all" speaking'
>
> .PHONY: all
> endef
> $(some_all)
>
> kylemoffett$ make all
> Makefile:7: *** multiple target patterns.  Stop.
>
> kylemoffett$

I am not sure if the second case is in fact a bug, or if the first case 
is merely
an unsupported feature, in which case I'd like to request such a 
feature.
On the other hand, perhaps there is a better way to do what I need to 
do. I
think it would be incredibly useful to be able to have variable 
expressions
that expand to targets very early on.  One application of this is to 
have a
function variable that generates a set of three or four different rules.
Depending on the results of shell executions I need different sets of 
rules
generated for each of a couple dozen files.

Cheers,
Kyle Moffett