cache coherency in DMA and MMIO

[Da Zheng]

Hello,

I try to make e1000 work with my porting of DDE Linux26. After I tested the
code, it seems the variables in the transmission queue, which are access by the
device with DMA, are not changed by the device after a packet is transmitted.
antrik suggested that it might be related to cache coherency.

I googled it and found an article
http://kerneltrap.org/mailarchive/linux-kernel/2008/4/29/1657814, which clearly
states "DMA (with a few very special cases as
exception that are beyond the scope of this document) is cache coherent with
the CPU on a PC. PCI MMIO regions and other similar pieces of device memory
are NOT cache coherent." Later it states that "On PCs, if the BIOS is not too
buggy, the BIOS will set up the MTRRs such that all regular memory is cachable,
and that all MMIO space is set to uncachable".

So does the driver need to consider about cache coherency problems on PC when
interacting with the external device?

Zheng Da