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[Bug ld/24226] Need advise on the binutils problem that generating wrong
From: |
liuyingying19 at huawei dot com |
Subject: |
[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend |
Date: |
Wed, 20 Feb 2019 01:28:51 +0000 |
https://sourceware.org/bugzilla/show_bug.cgi?id=24226
--- Comment #5 from GraceLiu <liuyingying19 at huawei dot com> ---
(In reply to Jim Wilson from comment #4)
> Yes, I'd call this a compiler bug. It is triggered when we have a long long
> inside a packed structure compiled for a 32-bit target, where the long long
> must be partially contained in the first word of the struct, in which case
> the long long has a 1 in 1K chance of getting an address that will generate
> an overflow when resolving relocations. That would explain why I haven't
> seen it before. Too many low chance conditions to trigger easily. The same
> problem could occur for a 64-bit target with a 128-bit type in a packed
> struct, but that is probably even more rare.
>
> There is still a linker issue here, in that the linker should generate an
> error when the reloc overflows and computes the wrong address.
>
> You can work around the compiler bug by forcing the variable to have 8-byte
> alignment. This can be done with an attribute
> struct S0 g_3030 __attribute__ ((aligned(8))) = {0,-9L,-0,-22553,7,-841,1};
> But that may be impractical if you have no easy way to identify the
> variables that need to be "fixed" to avoid the compiler problem.
>
> The compiler bug needs to be reported into the gcc bugzilla so it can be
> fixed there.
Thanks Jim for the advice.
I will try to file a bug to gcc bugzilla.
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- [Bug ld/24226] New: Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend, liuyingying19 at huawei dot com, 2019/02/18
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend, wilson at gcc dot gnu.org, 2019/02/18
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend, wilson at gcc dot gnu.org, 2019/02/18
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend, liuyingying19 at huawei dot com, 2019/02/18
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend, wilson at gcc dot gnu.org, 2019/02/19
- [Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend,
liuyingying19 at huawei dot com <=