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[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
From: |
h.IrfanAhmad at gmail dot com |
Subject: |
[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3 |
Date: |
Fri, 31 Jan 2014 18:40:45 +0000 |
https://sourceware.org/bugzilla/show_bug.cgi?id=16017
--- Comment #17 from Irfan Ahmad <h.IrfanAhmad at gmail dot com> ---
I missed an && in the ARM reference manual, :(
add ip, pc
Should be legal
addw ip, pc, #0
is not.
So we can rework my suggestion to:
1: f240 0c00 movw ip, #0x0000 ; Lower 16 bits of GOT entry offset
2: f2c0 0c00 movt ip, #0x0000 ; Upper 16 bits of GOT entry offset
3: 44fc add ip, pc
4: f8dc f000 ldr.w pc, [ip]
This will result in the same size as in the Solution 3 by Markus.
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