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[avrdude-dev] Xilinx JTAG cable


From: Tymm
Subject: [avrdude-dev] Xilinx JTAG cable
Date: Thu, 11 Nov 2004 23:51:22 -0700 (MST)

Hi,

To reduce the amount of cable switching I need to do on my parallel port, 
I looked at the UISP code for using a Xilinx JTAG cable for AVR 
programming, and (since I prefer avrdude :) ) used that & datasheet info 
to put together a programmer definition for it... I'd be happy to have it 
included in the standard conf file; it's a pretty standard 
buffer-on-the-end-of-a-wire device...

programmer
  id    = "xil";
  desc  = "Xilinx JTAG cable";
  type  = par;
  mosi  = 2;
  sck   = 3;
  reset = 4;
  buff  = 5;
  miso  = 13;
  vcc   = 6;
;

The "vcc" definition isn't really vcc (the cable gets its power from the 
programming circuit) but is necessary to switch one of the buffer lines 
(trying to add it to the "buff" lines doesn't work).

With this, TMS connects to RESET, TDI to MOSI, TDO to MISO and TCK to SCK 
(plus vcc/gnd of course)

Thanks,

-Tymm

-- 

"Do not doubt that a small group of dedicated individuals can change
the world. Indeed, that is all that ever has." -- Margaret Mead






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