[avr-gcc-list] Bug in inline asm optimization

[Killinger Sascha]

Hi guys,

i think there is a bug in gcc version
gcc version 3.3 20030421 (prerelease)

coming with the latest WinAVR release.


Consider the follwing code:

static inline void _delay_loop_1(unsigned char __count)
{
  asm volatile (
    "1: dec %0" "\n\t"
    "brne 1b"
    : "=r" (__count)
    : "0" (__count)
  );
}

int main(void)
{
  for(;;)
  {
    PORTB = 0;
    _delay_loop_1(100);
    PORTB = 0xff;
    _delay_loop_1(200);
  }
  return 0;
}


Compiling with
>avr-gcc -S -mmcu=atmega128 test.c -o test.s
the relevant generated code looks like:

.L6:
sts 56,__zero_reg__
ldi r24,lo8(100)
call _delay_loop_1
ldi r24,lo8(-1)
sts 56,r24
ldi r24,lo8(-56)
call _delay_loop_1
rjmp .L6


but after compiling with optimization enabled
>avr-gcc -S -Os -mmcu=atmega128 delayTest.c -o delayTest.s

gives

.L2:
out 56-0x20,__zero_reg__
/* #APP */
1: dec r25
brne 1b
/* #NOAPP */
ldi r24,lo8(-1)
out 56-0x20,r24
/* #APP */
1: dec r18
brne 1b
/* #NOAPP */
rjmp .L2


registers r25 and r18 never get loaded with 100 and 200.

Compiling with version
gcc version 3.3 20030310 (prerelease)
>avr-gcc -S -Os -mmcu=atmega128 delayTest.c -o delayTest.s

gives the correct code

.L2:
out 56-0x20,__zero_reg__
ldi r24,lo8(100)
/* #APP */
1: dec r24
brne 1b
/* #NOAPP */
ldi r24,lo8(-1)
out 56-0x20,r24
ldi r24,lo8(-56)
/* #APP */
1: dec r24
brne 1b
/* #NOAPP */
rjmp .L2


Can someone check this with the current cvs version?

/Sascha